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1. 发明申请

WO2007133280A3 SUPERJUNCTION POWER MOSFET 审中-公开
公开(公告)号：WO2007133280A3
公开(公告)日：2007-11-22
申请号：PCT/US2006/060826
申请日：2006-11-13
申请人： FREESCALE SEMICONDUCTOR INC. , DE FRESART, Edouard, D. , BAIRD, Robert, W. , QIN, Ganming
发明人： DE FRESART, Edouard, D. , BAIRD, Robert, W. , QIN, Ganming
IPC分类号： H01L29/80
摘要： Methods and apparatus are provided for TMOS devices (40), comprising multiple N-type source regions (50), electrically in parallel, located in multiple P-body regions (46) separated by N-type JFET regions (56) at a first surface. The gate (53) overlies the body channel regions (46) and the JFET region (56) lying between the body regions. The JFET region (56) communicates with an underlying drain region (42) via an N-epi region (44). Ion implantation and heat treatment are used to tailor the net active doping concentration N d in the JFET region (56) of length L acc and net active doping concentration N a in the P-body regions (46) of length L body so that a charge balance relationship (L body * N a ) = k 1 *(L acc * N d ) between P-body and JFET regions is satisfied, where k 1 is about 0.6 ≤ k 1 ≤ 1.4. The entire device (40) can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region (44) to the drain (42).

2. 发明申请

WO2006065531A3 CMOS NVM BITCELL AND INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2006065531A3
公开(公告)日：2006-06-22
申请号：PCT/US2005/043219
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PARRIS, Patrice , DE FRESART, Edouard, D. , DE SOUZA, Richard, D. , MORRISON, Jennifer, H.
发明人： PARRIS, Patrice , DE FRESART, Edouard, D. , DE SOUZA, Richard, D. , MORRISON, Jennifer, H.
IPC分类号： H01L21/336
摘要： A non-volatile memory bitcell structure (10) is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor (14) having a first capacitance value includes a first top plate (20), a first bottom plate (16), and a first dielectric (18) disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor (22) having a second capacitance value includes a second top plate (26), a second bottom plate (16), and a second dielectric (24) disposed in-between the second top plate and the second bottom plate. An element (16) of the first MIM capacitor (14) is electrically coupled in common with an element (16) of the second MIM capacitor (22). In addition, the first capacitance value is greater than the second capacitance value.

3. 发明申请

WO2006028793A1 METAL OXIDE SEMICONDUCTOR DEVICE INCLUDING A SHIELDING STRUCTURE FOR LOW GATE-DRAIN CAPACITANCE 审中-公开
标题翻译：金属氧化物半导体器件，包括用于低栅极电容的屏蔽结构
公开(公告)号：WO2006028793A1
公开(公告)日：2006-03-16
申请号：PCT/US2005/030772
申请日：2005-08-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PARRIS, Patrice , DE FRESART, Edouard, D.
发明人： PARRIS, Patrice , DE FRESART, Edouard, D.
IPC分类号： H01L21/00 , H01L21/30 , H01L21/822 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/42368
摘要： A semiconductor MOSFET device (70, 100), and method of fabricating the device, including a shielding structure (86, 210) for decreasing the gate-drain capacitance (CGD) without simultaneously increasing the gate resistance or the total device ON-state resistance (RDSON). The shielding structure (86, 210) is formed between a drain region (76, 106) and an active gate electrode (88, 118) in the form of a separate dummy gate (87) or a trench (212) having a material (214) formed therein. The shielding structure (86, 210) forms a capacitance "shield" between the gate (88, 118) and drain region (76, 106). The MOSFET device (70, 100) further includes a semiconductor material (74, 104) defining therein a drain region (76, 106), at least one body region (78, 108) formed in the semiconductor material (74, 104), at least one source region (80, 110) formed in each body region (78, 108), and an active gate electrode (88, 118) formed over the semiconductor material (74, 104).
摘要翻译：一种半导体MOSFET器件（70,100）以及制造该器件的方法，包括用于降低栅极 - 漏极电容（CGD）而不同时增加栅极电阻或总器件导通电阻的屏蔽结构（86,210）（RDSON）。屏蔽结构（86,210）形成在漏极区域（76,106）和具有单独的虚拟栅极（87）形式的有源栅电极（88,118）或具有材料的沟槽（212） 214）。屏蔽结构（86,210）在栅极（88,118）和漏极区域（76,106）之间形成电容“屏蔽”。 MOSFET器件（70,100）还包括在其中限定漏极区域（76,106）的半导体材料（74,104），形成在半导体材料（74,104）中的至少一个体区（78,108）形成在每个主体区域（78,108）中的至少一个源极区域（80,110）以及形成在所述半导体材料（74,104）上方的有源栅电极（88,118）。

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