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1. 发明申请

WO2016007135A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
标题翻译：基于负面差分电阻的记忆
公开(公告)号：WO2016007135A1
公开(公告)日：2016-01-14
申请号：PCT/US2014/045695
申请日：2014-07-08
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , RIOS, Rafael , YOUNG, Ian A.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.
摘要翻译：描述了一种存储位单元，包括：存储节点; 耦合到存储节点的存取晶体管; 电容器，其具有耦合到所述存储节点的第一端子; 以及耦合到存储节点的一个或多个负差分电阻器件，使得存储位单元不具有接地线或供电线之一或两者。

2. 发明申请

WO2017052621A1 MEMORY CELL WITH ASYMMETRIC CONDUCTION TO REDUCE WRITE MINIMUM OPERATING VOLTAGE (WVMIN) AND POWER CONSUMPTION 审中-公开
标题翻译：具有不对称导通的存储器单元以减少写入最小工作电压（WVMIN）和功耗
公开(公告)号：WO2017052621A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052352
申请日：2015-09-25
申请人： INTEL CORPORATION , MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
发明人： MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC分类号： H01L27/11
CPC分类号： H01L27/1104 , G11C7/02 , G11C11/412 , G11C11/419
摘要： Techniques for providing asymmetric conduction within an SRAM bit cell are provided and may substantially reduce energy consumption during write operations, and may also reduce the write minimum operation voltage (WVmin) for an SRAM device. In particular, some aspects disclosed herein include modifying or otherwise providing pull-up transistors configured to asymmetrically conduct to prevent current flow in a reverse direction, and more particularly, to prevent or otherwise mitigate current flowing back to Vcc during write operations. This can reduce voltage swings that would otherwise occur as internal bit cell nodes Q/Q# discharge, and thus, may reduce overall power consumption. The asymmetrical conducting characteristics may further reduce the magnitude of disturb currents within unselected cells (e.g., cells not selected for writes) and thus prevent the loss of data through inadvertent writes.
摘要翻译：提供了用于在SRAM位单元内提供不对称传导的技术，并且可以显着降低写入操作期间的能量消耗，并且还可以降低SRAM器件的写入最小工作电压（WVmin）。特别地，本文公开的一些方面包括修改或以其他方式提供被配置为不对称地导通的上拉晶体管，以防止在相反方向上的电流流动，更具体地，涉及防止或以其它方式缓解在写入操作期间流向Vcc的电流。这可以减少当内部位单元节点Q / Q＃放电时会发生的电压摆幅，从而可能降低总功耗。不对称导电特性可以进一步减小未选择的单元（例如，未被选择用于写入的单元）内的干扰电流的大小，从而通过无意写入来防止数据丢失。

3. 发明申请

WO2009006157A3 FLOATING BODY MEMORY ARRAY 审中-公开
标题翻译：浮动身体记忆阵列
公开(公告)号：WO2009006157A3
公开(公告)日：2009-04-09
申请号：PCT/US2008068184
申请日：2008-06-25
申请人： INTEL CORP , AVCI UYGAR E , CHANG PETER L D , SOMASEKHAR DINESH
发明人： AVCI UYGAR E , CHANG PETER L D , SOMASEKHAR DINESH
IPC分类号： H01L27/108
CPC分类号： G11C7/02 , G11C11/404 , G11C2211/4016
摘要： Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
摘要翻译：本文提供用于在阵列中的选定浮体单元的沟道上施加碰撞电离电位而不必将电位施加在其他未选中单元上的布局的实施例。

4. 发明申请

WO2019066875A1 FIELD EFFECT TRANSISTORS HAVING FERROELECTRIC OR ANTIFERROELECTRIC GATE DIELECTRIC STRUCTURE 审中-公开
公开(公告)号：WO2019066875A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054164
申请日：2017-09-28
申请人： INTEL CORPORATION , KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
发明人： KIM, Seiyon , AVCI, Uygar E. , HOWARD, Joshua M. , YOUNG, Ian A. , MORRIS, Daniel H.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51
摘要： Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

5. 发明申请

WO2015147849A1 TUNNELING FIELD EFFECT TRANSISTORS WITH A VARIABLE BANDGAP CHANNEL 审中-公开
标题翻译：具有可变带宽通道的隧道场效应晶体管
公开(公告)号：WO2015147849A1
公开(公告)日：2015-10-01
申请号：PCT/US2014/032117
申请日：2014-03-28
申请人： INTEL CORPORATION , AVCI, Uygar E. , NIKONOV, Dmitri E. , YOUNG, Ian A.
发明人： AVCI, Uygar E. , NIKONOV, Dmitri E. , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66977 , H01L25/16 , H01L29/0847 , H01L29/1025 , H01L29/1054 , H01L29/24 , H01L29/42384 , H01L29/42392 , H01L29/66356 , H01L29/66969 , H01L29/7391 , H01L29/78648 , H01L49/003
摘要： Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the variable bandgap channel may be dynamically altered by at least one of the application or withdrawal of a force, such as a voltage or electric field. In some embodiments the variable bandgap channel may be configured to modulate from an ON to an OFF state and vice versa in response to the application and/or withdrawal of a force. The variable bandgap channel may exhibit a bandgap that is smaller in the ON state than in the OFF state. As a result, the TFETs may exhibit one or more of relatively high on current, relatively low off current, and sub-threshold swing below 60 mV/decade.
摘要翻译：描述包括可变带隙通道的隧穿场效应晶体管（TFET）。在一些实施例中，可变带隙通道的一个或多个带隙特性可以通过施加或取出诸如电压或电场的力中的至少一个来动态改变。在一些实施例中，可变带隙通道可以被配置成响应于施加和/或撤回力而从接通到关闭状态和反之亦然。可变带隙通道可以表现出在ON状态下比在OFF状态下更小的带隙。结果，TFET可以呈现出一个或多个相对较高的导通电流，相对低的截止电流以及低于60mV /十倍的次阈值摆幅。

6. 发明申请

WO2016048306A1 SCALED TFET TRANSISTOR FORMED USING NANOWIRE WITH SURFACE TERMINATION 审中-公开
标题翻译：使用纳米线表面终止形成的尺寸TFET晶体管
公开(公告)号：WO2016048306A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057258
申请日：2014-09-24
申请人： INTEL CORPORATION , AVCI, Uygar E. , RIOS, Rafael , KUHN, Kelin J. , YOUNG, Ian A. , WEBER, Justin R.
发明人： AVCI, Uygar E. , RIOS, Rafael , KUHN, Kelin J. , YOUNG, Ian A. , WEBER, Justin R.
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0669 , H01L29/0673 , H01L29/068 , H01L29/16 , H01L29/2003 , H01L29/24 , H01L29/66795 , H01L29/7391
摘要： Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.
摘要翻译：描述了一种TFET，其包括：具有用于形成源极和漏极区域的掺杂区域的纳米线和用于耦合到栅极区域的未掺杂区域; 以及形成在所述纳米线上的第一端接材料; 以及形成在纳米线的与栅极和源极区域重叠的部分上的第二端接材料。描述了另一个TFET，其包括：具有用于形成源极和漏极区域的掺杂区域的纳米线的第一部分和用于耦合到栅极区域的未掺杂区域; 所述纳米线的第二部分垂直于所述第一部分延伸，所述第二部分形成在所述栅极和源极区域旁边; 以及形成在纳米线的第一和第二部分上的端接材料。

7. 发明申请

WO2015099686A1 HETEROGENEOUS POCKET FOR TUNNELING FIELD EFFECT TRANSISTORS (TFETS) 审中-公开
标题翻译：用于隧道场效应晶体管（TFETS）的异质密封
公开(公告)号：WO2015099686A1
公开(公告)日：2015-07-02
申请号：PCT/US2013/077604
申请日：2013-12-23
申请人： INTEL CORPORATION , AVCI, Uygar E. , KOTLYAR, Roza , DEWEY, Gilbert , CHU-KUNG, Benjamin , YOUNG, Ian A.
发明人： AVCI, Uygar E. , KOTLYAR, Roza , DEWEY, Gilbert , CHU-KUNG, Benjamin , YOUNG, Ian A.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/125 , G11C5/06 , H01L29/0669 , H01L29/165 , H01L29/205 , H01L29/7391 , H01L29/7831
摘要： Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to increase a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.
摘要翻译：本文所述的本发明的实施例包括具有漏极区域，具有与漏极区域相反的导电类型的源极区域的沟道场效应晶体管（TFET），设置在源极区域和漏极区域之间的沟道区域，栅极设置在沟道区域和设置在源区域和沟道区域的结点附近的异质袋。异质袋包括不同于沟道区的半导体材料，并且包括小于沟道区中的带隙的隧道势垒，并且在施加到栅极的电压时在沟道区中形成量子阱以增加通过TFET晶体管的电流高于阈值电压。

8. 发明申请

WO2009006157A2 FLOATING BODY MEMORY ARRAY 审中-公开
标题翻译：浮动身体记忆阵列
公开(公告)号：WO2009006157A2
公开(公告)日：2009-01-08
申请号：PCT/US2008/068184
申请日：2008-06-25
申请人： INTEL CORPORATION , AVCI, Uygar, E. , CHANG, Peter, L., D. , SOMASEKHAR, Dinesh
发明人： AVCI, Uygar, E. , CHANG, Peter, L., D. , SOMASEKHAR, Dinesh
IPC分类号： H01L27/108
CPC分类号： G11C7/02 , G11C11/404 , G11C2211/4016
摘要： Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
摘要翻译：本文提供了用于在阵列中的选定浮体单元的通道上施加冲击电离电位的布局的实施例，而不必将电位施加在其它未选择的单元上。

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