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1. 发明申请

WO0233706A3 NOISE SUPPRESSION FOR OPEN BIT LINE DRAM ARCHITECTURES 审中-公开
标题翻译：用于打开位线DRAM架构的噪声抑制
公开(公告)号：WO0233706A3
公开(公告)日：2003-04-17
申请号：PCT/US0131159
申请日：2001-10-03
申请人： INTEL CORP , LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
发明人： LU SHIH-LIEN , SOMASEKHAR DINESH , DE VIVEK
IPC分类号： G11C20060101 , G11C7/02 , G11C11/4094 , G11C11/4097 , H01L20060101 , G11C7/12 , G11C7/14 , G11C7/18 , G11C11/4099 , H01L27/108
CPC分类号： G11C11/4097 , G11C7/02 , G11C11/4094
摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.
摘要翻译：开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。在一种方法中，提供虚拟单元和参考单元用于执行信号注入。本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

2. 发明申请

WO2018182755A1 INNOVATIVE WAY TO DESIGN SILICON TO OVERCOME RETICLE LIMIT 审中-公开
公开(公告)号：WO2018182755A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025663
申请日：2017-04-01
申请人： INTEL CORPORATION , HOSSAIN, MD Altaf , SOMASEKHAR, Dinesh , SUBBAREDDY, Dheeraj
发明人： HOSSAIN, MD Altaf , SOMASEKHAR, Dinesh , SUBBAREDDY, Dheeraj
IPC分类号： H01L25/065 , H01L25/07 , H01L23/532 , H01L23/00
摘要： Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.

3. 发明申请

WO2010074948A2 INTEGRATED CIRCUIT, 1T-1C EMBEDDED MEMORY CELL CONTAINING SAME, AND METHOD OF MANUFACTURING 1T-1C MEMORY CELL FOR EMBEDDED MEMORY APPLICATION 审中-公开
标题翻译：集成电路，1T-1C嵌入式存储器单元以及制造用于嵌入式存储器应用的1T-1C存储器单元的方法
公开(公告)号：WO2010074948A2
公开(公告)日：2010-07-01
申请号：PCT/US2009067066
申请日：2009-12-08
申请人： INTEL CORP , DOYLE BRIAN S , SOMASEKHAR DINESH , DEWEY GILBERT , SURI SATYARTH
发明人： DOYLE BRIAN S , SOMASEKHAR DINESH , DEWEY GILBERT , SURI SATYARTH
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/90 , H01L27/10894 , H01L27/10897
摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.
摘要翻译：集成电路包括半导体衬底（110），半导体衬底上的导电层（120）以及至少部分嵌入半导体衬底内的电容器（130），使得电容器完全位于导电层下方。存储节点电压位于电容器的外层（132）上。在相同或另一个实施例中，集成电路可以充当包括半导体衬底，半导体衬底之上的电绝缘堆栈（160），包括源极/漏极区域（142）的晶体管（140）的1T-1C嵌入式存储器单元）在半导体衬底和半导体衬底上方的栅极区域（141）之间;沟槽（111），延伸穿过电绝缘层并进入半导体衬底;位于沟槽内的第一电绝缘层（131）;以及电容器位于第一电绝缘层内部的沟槽内。

4. 发明申请

WO2009006157A2 FLOATING BODY MEMORY ARRAY 审中-公开
标题翻译：浮动身体记忆阵列
公开(公告)号：WO2009006157A2
公开(公告)日：2009-01-08
申请号：PCT/US2008/068184
申请日：2008-06-25
申请人： INTEL CORPORATION , AVCI, Uygar, E. , CHANG, Peter, L., D. , SOMASEKHAR, Dinesh
发明人： AVCI, Uygar, E. , CHANG, Peter, L., D. , SOMASEKHAR, Dinesh
IPC分类号： H01L27/108
CPC分类号： G11C7/02 , G11C11/404 , G11C2211/4016
摘要： Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
摘要翻译：本文提供了用于在阵列中的选定浮体单元的通道上施加冲击电离电位的布局的实施例，而不必将电位施加在其它未选择的单元上。

5. 发明申请

WO2013002884A1 6F2 DRAM CELL 审中-公开
公开(公告)号：WO2013002884A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/034431
申请日：2012-04-20
申请人： INTEL CORPORATION , WANG, Yih , WEBB, M. Clair , LINDERT, Nick , SIVAKUMAR, Swaminathan , ZHANG, Kevin X. , SOMASEKHAR, Dinesh
发明人： WANG, Yih , WEBB, M. Clair , LINDERT, Nick , SIVAKUMAR, Swaminathan , ZHANG, Kevin X. , SOMASEKHAR, Dinesh
IPC分类号： G11C5/02 , G11C5/06 , G11C11/40 , H01L27/108
CPC分类号： H01L27/10814 , H01L27/0207 , H01L27/10891
摘要： A 6F 2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.
摘要翻译：描述了具有成对单元的6F2 DRAM单元。在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。虚拟字线由具有有利于p沟道器件的功函数的金属制成。

6. 发明申请

WO2012087455A3 HIERARCHICAL DRAM SENSING 审中-公开
标题翻译：分层DRAM感应
公开(公告)号：WO2012087455A3
公开(公告)日：2012-12-13
申请号：PCT/US2011060861
申请日：2011-11-15
申请人： INTEL CORP , SOMASEKHAR DINESH , PANDYA GUNJAN , ZHANG KEVIN , HAMZAOGLU FATIH , SRINIVASAN BALAJI , GHOSH SWAROOP , MESUT METERELLIYOZ
发明人： SOMASEKHAR DINESH , PANDYA GUNJAN , ZHANG KEVIN , HAMZAOGLU FATIH , SRINIVASAN BALAJI , GHOSH SWAROOP , MESUT METERELLIYOZ
IPC分类号： G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4097 , G11C7/065 , G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
摘要翻译：采用本地位线对和全局位线的分级DRAM感测装置和方法。字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。选择本地位线之一用于耦合到全局位线和全局读出放大器。集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

7. 发明申请

WO2012087473A2 NOR LOGIC WORD LINE SELECTION 审中-公开
标题翻译： NOR逻辑字线选择
公开(公告)号：WO2012087473A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/061607
申请日：2011-11-21
申请人： INTEL CORPORATION , GHOSH, Swaroop , SOMASEKHAR, Dinesh , SRINIVASAN, Balaji , HAMZAOGLU, Fatih
发明人： GHOSH, Swaroop , SOMASEKHAR, Dinesh , SRINIVASAN, Balaji , HAMZAOGLU, Fatih
IPC分类号： G11C11/4063
CPC分类号： G11C11/4085 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A NOR architecture for selecting a word line driver in a DRAM is disclosed. Complements of separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
摘要翻译：公开了一种用于在DRAM中选择字线驱动器的NOR架构。用于在低，中和高范围内分别解码的地址的完成用于选择最终的字线驱动器。字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且对于所选择的字线为比正向电位更大的正电位。

8. 发明申请

WO2011146823A2 METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE 审中-公开
标题翻译：在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
公开(公告)号：WO2011146823A2
公开(公告)日：2011-11-24
申请号：PCT/US2011/037319
申请日：2011-05-20
申请人： INTEL CORPORATION , WILKERSON, Christopher B. , WU, Wei , ALAMELDEEN, Alaa R. , LU, Shih-Lien , CHISHTI, Zeshan A. , SOMASEKHAR, Dinesh
发明人： WILKERSON, Christopher B. , WU, Wei , ALAMELDEEN, Alaa R. , LU, Shih-Lien , CHISHTI, Zeshan A. , SOMASEKHAR, Dinesh
CPC分类号： G06F11/1064
摘要： A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.
摘要翻译：提供了一种使用具有低存储和复杂度开销的多位错误校正码（ECC）的高速缓冲存储器系统。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。

9. 发明申请

WO2010078051A2 EMBEDDED MEMORY CELL AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：嵌入式存储单元及其制造方法
公开(公告)号：WO2010078051A2
公开(公告)日：2010-07-08
申请号：PCT/US2009/068524
申请日：2009-12-17
申请人： INTEL CORPORATION , KAVALIEROS, Jack T. , MUKHERJEE, Niloy , DEWEY, Gilbert , SOMASEKHAR, Dinesh , DOYLE, Brian S.
发明人： KAVALIEROS, Jack T. , MUKHERJEE, Niloy , DEWEY, Gilbert , SOMASEKHAR, Dinesh , DOYLE, Brian S.
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

10. 发明申请

WO2014051545A1 DIGITALLY PHASE LOCKED LOW DROPOUT REGULATOR 审中-公开
标题翻译：数字相位锁定低压差型稳压器
公开(公告)号：WO2014051545A1
公开(公告)日：2014-04-03
申请号：PCT/US2012/057066
申请日：2012-09-25
申请人： RAYCHOWDHURY, Arijit , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
发明人： RAYCHOWDHURY, Arijit , SOMASEKHAR, Dinesh , TSCHANZ, James W. , DE, Vivek K.
IPC分类号： G05F1/10 , G05F1/40
CPC分类号： G05F1/577 , G05F1/468 , G05F1/56 , G06F1/06 , G06F1/26 , H03L7/085 , Y10T307/406
摘要： Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
摘要翻译：描述了一种装置，包括：第一振荡器，用于产生第一时钟信号第二振荡器以产生第二时钟信号; 相位频率检测器，用于检测第一和第二时钟信号之间的相位差，并产生相位差; 以及耦合到负载的输出级，以根据相位差产生用于负载的电源。

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