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1. 发明申请

WO2015167626A1 ADAPTIVE LOW SKEW CLOCKING ARCHITECTURE 审中-公开
标题翻译：自适应低穗式钟表结构
公开(公告)号：WO2015167626A1
公开(公告)日：2015-11-05
申请号：PCT/US2015/011220
申请日：2015-01-13
申请人： XILINX, INC.
发明人： GAIDE, Brian, C.
IPC分类号： G06F1/10
CPC分类号： H03K5/159 , G06F1/10 , H03K2005/00078
摘要： A system includes: an initial clock region (120); a first adjacent clock region (120') adjacent to the initial clock region; a spine (150, 150a) coupled to receive a clock signal from a clock; and a first phase detector (160) to detect a difference in phase between the initial clock region and the first adjacent clock region. The initial clock region comprises an initial delay element (170) coupled to the spine and to the first phase detector.
摘要翻译：系统包括：初始时钟区域（120）; 与初始时钟区域相邻的第一相邻时钟区域（120'）; 耦合以从时钟接收时钟信号的脊（150,150a）; 以及用于检测初始时钟区域和第一相邻时钟区域之间的相位差的第一相位检测器（160）。初始时钟区域包括耦合到脊柱和第一相位检测器的初始延迟元件（170）。

2. 发明申请

WO2014209437A1 WINDOWING FOR HIGH-SPEED ANALOG-TO-DIGITAL CONVERSION 审中-公开
标题翻译： WINDOWING高速模拟数字转换
公开(公告)号：WO2014209437A1
公开(公告)日：2014-12-31
申请号：PCT/US2014/021346
申请日：2014-03-06
申请人： XILINX, INC.
发明人： FARLEY, Brendan , HUDNER, James , BOGUE, Ivan , CAREY, Declan , WALSH, Darragh , ERETT, Marc
IPC分类号： H03M1/00 , H03M1/36
CPC分类号： H03M1/12 , H03M1/002 , H03M1/365
摘要： An analog-to-digital converter ("ADC") (300) is disclosed. The ADC includes a bank (310) of comparators (312) and a window controller (315). The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
摘要翻译：公开了一种模拟 - 数字转换器（“ADC”）（300）。 ADC包括比较器（312）的组（310）和窗口控制器（315）。窗口控制器耦合到比较器组，以选择性地激活与窗口大小相关联的比较器组的第一比较器，并且选择性地使比较器组的第二比较器失活。

3. 发明申请

WO2014028066A1 FLEXIBLE SIZED DIE FOR USE IN MULTI-DIE INTEGRATED CIRCUIT 审中-公开
标题翻译：灵活尺寸的DIE用于多集成电路
公开(公告)号：WO2014028066A1
公开(公告)日：2014-02-20
申请号：PCT/US2013/036610
申请日：2013-04-15
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L25/065 , H01L23/14 , H01L21/66 , G01R31/28
CPC分类号： G01R31/28 , H01L21/78 , H01L22/32 , H01L23/145 , H01L23/147 , H01L23/49827 , H01L25/0652 , H01L25/0655 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/14 , H01L2924/14253 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/1435 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/0105
摘要： An integrated circuit (IC) structure (100) can include a first die (110) and a second die (115). The second die can include a first base unit (120) and a second base unit (130). Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer (105). The interposer includes a first plurality of inter-die wires (215A) coupling the first die to the first base unit, a second plurality of inter-die wires (215C) coupling the first die to the second base unit, and a third plurality of inter-die wires (215D) coupling the first base unit to the second base unit. In some embodiments, the first and second base units are identical.
摘要翻译：集成电路（IC）结构（100）可以包括第一管芯（110）和第二管芯（115）。第二模具可以包括第一基座单元（120）和第二基座单元（130）。第一基座单元和第二基座单元中的每一个是独立的，并且在第二模具内的第一基座单元和第二基座单元之间没有信号通过。 IC结构可以包括插入件（105）。插入器包括将第一管芯耦合到第一基板单元的第一多个管芯间线（215A），将第一管芯连接到第二基座单元的第二多个管芯间线（215C），以及第三多个管芯将第一基座单元连接到第二基座单元的芯片间导线（215D）。在一些实施例中，第一和第二基座单元是相同的。

4. 发明申请

WO2014011281A1 METHODS FOR FLIP CHIP STACKING 审中-公开
标题翻译： FLIP芯片堆叠方法
公开(公告)号：WO2014011281A1
公开(公告)日：2014-01-16
申请号：PCT/US2013/036212
申请日：2013-04-11
申请人： XILINX, INC.
发明人： KWON, Woon-Seong , RAMALINGAM, Suresh
IPC分类号： H01L23/14 , H01L23/498 , H01L23/00 , H01L25/065
CPC分类号： H01L21/4853 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L24/75 , H01L24/81 , H01L24/97 , H01L25/0655 , H01L2224/131 , H01L2224/13147 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/75744 , H01L2224/7598 , H01L2224/75983 , H01L2224/75987 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/3511 , H01L2924/014 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2224/81 , H01L2924/00014
摘要： A method for flip chip stacking includes forming (201) a cavity wafer (301) comprising a plurality of cavities (303) and a pair of corner guides (305), placing (203) a through-silicon-via (TSV) interposer (103) with solder bumps (107) coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated between the pair of corner guides, placing (205) an integrated circuit (IC) die (109) on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit (113), removing (207) the stacked interposer unit from the cavity wafer, and bonding (209) the solder bumps of the stacked interposer unit to an organic substrate (101) such that the stacked interposer unit and the organic substrate form a flip chip (300).
摘要翻译：一种用于倒装芯片堆叠的方法包括形成（201）包括多个空腔（303）和一对拐角引导件（305）的空腔晶片（301），放置（203）穿硅通孔（TSV）插入器 103），其中焊料凸块（107）耦合到空腔晶片上的TSV插入器的表面，使得焊料凸块位于多个空腔中，并且TSV插入件位于一对拐角引导件之间，放置（205）在所述TSV插入器的另一表面上的集成电路（IC）管芯（109），使得所述IC管芯，所述TSV插入件和所述焊料凸块形成堆叠的中介层单元（113），将所述堆叠的中介层单元将所述堆叠的中介层单元的所述焊料凸块接合（209）到有机基板（101），使得所述堆叠的中介层单元和所述有机基板形成倒装芯片（300）。

5. 发明申请

WO2013081683A1 CIRCUIT FOR AND METHOD OF ENABLING THE TRANSFER OF DATA BY AN INTEGRATED CIRCUIT 审中-公开
标题翻译：通过集成电路实现数据传输的电路和方法
公开(公告)号：WO2013081683A1
公开(公告)日：2013-06-06
申请号：PCT/US2012/051505
申请日：2012-08-17
申请人： XILINX, INC. , KULKARNI, Sanjay, A.
发明人： KULKARNI, Sanjay, A.
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , G06F13/4291 , G11C7/10
摘要： A circuit for enabling the transfer of data by an integrated circuit is described. The circuit comprises a non-volatile memory array (610) coupled to receive a clock signal and having a plurality of memory elements storing data; and a control circuit (404) coupled to the non-volatile memory array, the control circuit enabling uni-directional transfer of data on a plurality of signal lines between the non-volatile memory array and the control circuit in a first mode and bi-directional transfer of data in a second mode; wherein the control circuit controls the transfer of data on the plurality of signal lines between the non- volatile memory array and the control circuit in the first mode on both the rising and falling edges of the clock signal. A method of enabling the transfer of data by an integrated circuit device is also described.
摘要翻译：描述了一种能够通过集成电路传输数据的电路。电路包括耦合以接收时钟信号并且具有存储数据的多个存储器元件的非易失性存储器阵列（610）以及耦合到所述非易失性存储器阵列的控制电路（404），所述控制电路能够以第一模式和第二模式在所述非易失性存储器阵列和所述控制电路之间的多条信号线上单向传输数据，以第二模式定向传送数据; 其中控制电路在时钟信号的上升沿和下降沿控制在第一模式中的非易失性存储器阵列与控制电路之间的多条信号线上的数据传输。还描述了能够通过集成电路器件传输数据的方法。

6. 发明申请

WO2013058831A1 PARALLEL PROCESSING OF NETWORK PACKETS 审中-公开
标题翻译：网络分组的并行处理
公开(公告)号：WO2013058831A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/038384
申请日：2012-05-17
申请人： XILINX, INC. , BREBNER, Gordon, J.
发明人： BREBNER, Gordon, J.
IPC分类号： H04L12/931
CPC分类号： H04L12/56
摘要： A packet processing circuit includes a plurality of header extraction circuits (208-214), and a scheduling circuit (206) coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus (202) having a plurality of data lanes (302). In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request (304), and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes (306).
摘要翻译：分组处理电路包括多个报头提取电路（208-214），以及耦合到多个报头提取电路的调度电路（206）。调度电路被配置为从具有多个数据通道（302）的数据总线（202）接收一个或多个请求以提取相应分组的头部数据。响应于每个请求，调度电路确定包含由请求（304）指定的相应报头的多个数据通道的第一子集，并且分配多个标题提取电路中的相应一个以从多个数据通道中的第一子集（306）。

7. 发明申请

WO2013002844A1 INTEGRATED CIRCUIT DESIGN USING THROUGH SILICON VIAS 审中-公开
标题翻译：集成电路采用硅六角形设计
公开(公告)号：WO2013002844A1
公开(公告)日：2013-01-03
申请号：PCT/US2012/021416
申请日：2012-01-16
申请人： XILINX, INC. , RAHMAN, Arifur
发明人： RAHMAN, Arifur
IPC分类号： H01L25/07 , H01L25/065 , H01L23/522
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/481 , H01L23/5384 , H01L25/0652 , H01L25/072 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17181 , H01L2224/48145 , H01L2224/48227 , H01L2225/06513 , H01L2225/06544 , H01L2225/06572 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/00012
摘要： In an integrated circuit (IC) structure, the positioning of through silicon vias (TSVs) in terms of the physical layout of circuitry is described. An IC structure can include a plurality of first circuit elements (D1, G1, & S; 702, 706, 710, & 714; or 702, 706, 704, & 708); a plurality of second circuit elements (D2, G2, & S; 704, 708, 712, & 716; or 710, 714, 712, & 716); a plurality of first TSVs (410 & 510; 605-620; or 720-734); and a plurality of second TSVs (415 & 505; 625-640; or 736-750). The first and second circuit elements and the first and second TSVs together comprise a circuit block configuration. The circuit block configuration is symmetric with respect to at least one axis of symmetry. At least one of the first TSVs is a dummy TSV without which the circuit block configuration would not be symmetric.
摘要翻译：在集成电路（IC）结构中，描述了通过硅通孔（TSV）在电路的物理布局方面的定位。 IC结构可以包括多个第一电路元件（D1，G1，＆amp; S; 702,706,710，＆714;或702,706,704，＆708）; 多个第二电路元件（D2，G2，＆S; 704,708,712和716;或710,714,712和716）; 多个第一TSV（410和510; 605-620;或720-734）; 和多个第二TSV（415和505; 625-640;或736-750）。第一和第二电路元件以及第一和第二TSV一起包括电路块配置。电路块结构相对于至少一个对称轴对称。第一TSV中的至少一个是虚拟TSV，其中电路块配置不会对称。

8. 发明申请

WO2012121880A1 CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：在集成电路中校准器件性能
公开(公告)号：WO2012121880A1
公开(公告)日：2012-09-13
申请号：PCT/US2012/025976
申请日：2012-02-21
申请人： XILINX, INC. , SADOUGHI, Sharmin , AHN, Jae-gyung
发明人： SADOUGHI, Sharmin , AHN, Jae-gyung
IPC分类号： H01L21/8234 , H01L21/66 , G01R31/317
CPC分类号： H03K17/18 , H01L22/22 , H01L2924/0002 , H03K17/12 , H01L2924/00
摘要： A multi-fingered device (105) for implementation within an integrated circuit can include a first finger configured to remain active; a second finger that is initially deactivated concurrent with the first finger being active; and a finger activation circuit (125) configured to selectively activate the second finger of the multi- fingered device (105) in response to determining that a measure of degradation for the multi-fingered device (105) meets a degradation threshold.
摘要翻译：用于在集成电路内实现的多指装置（105）可以包括被配置为保持活动的第一手指; 最初与第一手指同时激活的第二手指被激活; 以及手指激活电路（125），其被配置为响应于确定所述多指装置（105）的劣化度量达到劣化阈值而选择性地激活所述多指装置（105）的所述第二手指。

9. 发明申请

WO2012067733A1 CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY 审中-公开
标题翻译：分类软错误的关键性和基于关键性的软错误
公开(公告)号：WO2012067733A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/055593
申请日：2011-10-10
申请人： XILINX, INC.
发明人： RODRIGUEZ, Alfred, L. , POSSLEY, Nicholas, J. , BOSHEARS, Kevin , LESEA, Austin, H. , HUSSEIN, Jameel
IPC分类号： G06F11/10 , H03K19/00
CPC分类号： G06F11/106
摘要： Methods and systems mitigate a soft error in an integrated circuit (200, 302). A map (350, 352) is stored (112) that specifies a criticality class for each storage bit (332, 334) in the integrated circuit. A mitigation technique is associated with each criticality class. The soft error is detected (114) in a corrupted one of the storage bits. The mitigation technique is performed (116) that is associated with the criticality class specified in the map for the corrupted storage bit.
摘要翻译：方法和系统减轻集成电路（200,302）中的软错误。存储映射（350,352）（112），其指定集成电路中的每个存储位（332,334）的临界级。缓解技术与每个临界级相关联。在损坏的一个存储位中检测到软错误（114）（114）。执行缓解技术（116），其与对于损坏的存储位的映射中指定的关键性类相关联。

10. 发明申请

WO2012003008A1 INTEGRATED CIRCUIT FOR AND METHOD OF TESTING DIE -TO -DIE BONDING 审中-公开
标题翻译：集成电路和测试DIE-TO-BINING的方法
公开(公告)号：WO2012003008A1
公开(公告)日：2012-01-05
申请号：PCT/US2011/021558
申请日：2011-01-18
申请人： XILINX, INC.
发明人： RAHMAN, Arifur
IPC分类号： G01R31/28 , H01L21/66 , H01L25/065
CPC分类号： G01R31/318513 , G01R31/2853 , H01L22/14 , H01L22/20 , H01L22/22 , H01L22/32 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： An integrated circuit (100) includes a first die (105, 110), a second die (115) on which the first die may be disposed, a plurality of inter-die connections (205, 205A, 205B) coupling the first die to the second die, and a plurality of probe pads (120, 120A, 120B, 120C, 120D, 120E), where each probe pad is coupled (305, 310, 405, 410) to at least one of the inter-die connections. The first die may be configured to establish an internal connection (315, 415, 420, 515) coupling the first probe pad to the second probe pad. In some embodiments, each probe pad is coupled to a micro-bump (210), and the internal connections couple the micro-bumps one to another. Some embodiments utilize through silicon vias extending through the second die. Methods of testing the described integrated circuits are also disclosed.
摘要翻译：集成电路（100）包括第一管芯（105,110），可以设置第一管芯的第二管芯（115），将第一管芯与第一管芯连接的多个管芯间连接（205,205A，205B）第二管芯和多个探针焊盘（120,120A，120B，120C，120D，120E），其中每个探针焊盘耦合到至少一个管芯间连接（305,310,405,410）。第一管芯可以被配置成建立将第一探针焊盘耦合到第二探针焊盘的内部连接（315,415,420,515）。在一些实施例中，每个探针垫耦合到微凸起（210），并且内部连接将微凸块彼此连接。一些实施例通过延伸穿过第二管芯的硅通孔。还公开了测试所描述的集成电路的方法。

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