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81. 发明申请

WO2017213639A1 QUANTUM DOT DEVICES 审中-公开
公开(公告)号：WO2017213639A1
公开(公告)日：2017-12-14
申请号：PCT/US2016/036319
申请日：2016-06-08
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , ROBERTS, Jeanette M. , MICHALAK, David J. , LE, Van H. , YOSCOVITS, Zachary R. , CLARKE, James S.
IPC分类号： H01L29/778 , H01L29/66 , H01L29/12
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

82. 发明申请

WO2017188951A1 INTEGRATED CIRCUIT STRUCTURES WITH EXTENDED CONDUCTIVE PATHWAYS 审中-公开
标题翻译：具有扩展导电路径的集成电路结构
公开(公告)号：WO2017188951A1
公开(公告)日：2017-11-02
申请号：PCT/US2016/029692
申请日：2016-04-28
申请人： INTEL CORPORATION
发明人： CHEW, Yen Hsiang
IPC分类号： H01L23/48 , H01L21/60 , H01L23/28 , H01L23/488 , H01L25/065
摘要： Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side.
摘要翻译：本文公开了具有延伸的导电路径的集成电路（IC）结构以及相关的结构，装置和方法。例如，在一些实施例中，IC结构可以包括具有器件侧和相对的背侧的管芯; 放置在背面的模制化合物; 以及从背面延伸到模具中并从背面延伸到模具化合物中的导电通路。

83. 发明申请

WO2017171738A1 HYBRID MICROELECTRONIC SUBSTRATES 审中-公开
标题翻译：混合微电子基片
公开(公告)号：WO2017171738A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/024827
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： STARKSTON, Robert , SANKMAN, Robert L. , MOKLER, Scott M. , STAMEY, Richard Christopher , ALUR, Amruthavalli Pallavi
IPC分类号： H01L23/48 , H01L23/498 , H01L23/485 , H01L23/488
摘要： Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.
摘要翻译：本文公开了混合微电子衬底以及相关器件和方法。在一些实施例中，混合微电子衬底可以包括在第一表面处具有凹槽的低密度微电子衬底以及设置在凹槽中并且经由焊料耦合到凹槽底部的高密度微电子衬底。

84. 发明申请

WO2017160284A1 STAIRSTEP INTERPOSERS WITH INTEGRATED SHIELDING FOR ELECTRONICS PACKAGES 审中-公开
标题翻译： STAIRSTEP INTERPOSERS集成屏蔽电子套件
公开(公告)号：WO2017160284A1
公开(公告)日：2017-09-21
申请号：PCT/US2016/022549
申请日：2016-03-16
申请人： INTEL CORPORATION
发明人： CHEAH, Bok Eng , LO, Hungying Louis
IPC分类号： H01L25/065 , H01L23/60 , H01L23/48
摘要： Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may include: an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate, wherein a first thickness of the insulating material between the first step surface and the bottom surface is greater than a second thickness of the insulating material between the second step surface and the bottom surface; a conductive signal pathway extending from the first step surface to the bottom surface; and a conductive shield disposed within the insulating material to shield the conductive signal pathway.
摘要翻译：这里公开了具有集成导电屏蔽的阶梯式中介层以及相关的组件和技术。在一些实施例中，插入件可以包括：具有阶梯结构的绝缘材料，该阶梯结构具有第一台阶表面，第二台阶表面以及面对封装基板的底表面，其中第一台阶表面并且所述底表面大于所述第二台阶表面和所述底表面之间的所述绝缘材料的第二厚度; 从第一台阶表面延伸到底表面的导电信号路径; 以及设置在绝缘材料内以屏蔽导电信号路径的导电屏蔽。

85. 发明申请

WO2017146720A1 WAFER RETAINER RINGS FOR CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译：用于化学机械抛光的晶片固定环
公开(公告)号：WO2017146720A1
公开(公告)日：2017-08-31
申请号：PCT/US2016/019722
申请日：2016-02-26
申请人： INTEL CORPORATION
发明人： TREGUB, Alexander
IPC分类号： H01L21/304
CPC分类号： B24B37/32 , B24B53/017
摘要： Disclosed herein are wafer retainer rings for chemical mechanical polishing (CMP) systems. In some embodiments, a wafer retainer ring may include a top surface; a bottom surface; an inner surface; an outer surface; and a plurality of openings extending from the inner surface to the outer surface, wherein individual openings of the plurality of openings are disposed between and spaced away from the top surface and the bottom surface. During use, the top surface may contact a polishing pad, and slurry may flow through the openings to help polish a wafer retained in the wafer retainer ring.
摘要翻译：这里公开了用于化学机械抛光（CMP）系统的晶片保持环。在一些实施例中，晶片固定环可以包括顶面; 底面; 内表面; 外表面; 以及从所述内表面延伸到所述外表面的多个开口，其中所述多个开口中的各个开口设置在所述顶表面和所述底表面之间并且与所述顶表面和所述底表面间隔开。在使用期间，顶面可以接触抛光垫，并且浆料可以流过开口以帮助抛光保留在晶片固定环中的晶片。

86. 发明申请

WO2017146677A1 CONDITIONING DISKS FOR CHEMICAL MECHANICAL POLISHING 审中-公开
标题翻译：化学机械抛光用空调盘
公开(公告)号：WO2017146677A1
公开(公告)日：2017-08-31
申请号：PCT/US2016/019005
申请日：2016-02-23
申请人： INTEL CORPORATION
发明人： TREGUB, Alexander , O'FARRELL, Denis J.
IPC分类号： H01L21/304
CPC分类号： B24B53/00
摘要： Disclosed herein are chemical mechanical polishing (CMP) conditioning disks, and related systems and techniques. For example, in some embodiments, a CMP conditioning disk may include: a support; a first pedestal extending from the support, the first pedestal having a first surface roughness (SR); and a second pedestal extending from the support, the second pedestal having a second SR different from the first SR.
摘要翻译：本文公开了化学机械抛光（CMP）调节盘，以及相关的系统和技术。例如，在一些实施例中，CMP修整盘可以包括：支撑件; 第一基座，其从所述支撑件延伸，所述第一基座具有第一表面粗糙度（SR）;第二基座，以及从支撑件延伸的第二基座，第二基座具有与第一SR不同的第二SR。

87. 发明申请

WO2017112136A1 INTEGRATED CIRCUIT PACKAGE SUPPORT STRUCTURES 审中-公开
标题翻译：集成电路封装支撑结构
公开(公告)号：WO2017112136A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/062146
申请日：2016-11-16
申请人： INTEL CORPORATION
发明人： HUI, Michael , YEE, Rashelle , THIBADO, Jonathan , CARTER, Daniel P. , FERGUSON, Shelby , VALPIANI, Anthony P. , AOKI, Russell S. , CARSTENS, Jonathon Robert , JASNIEWSKI, Joseph J. , KOFSTAD, Harvey R. , BRAZEL, Michael , CLACK, Tracy , VOGMAN, Viktor , WOODCOCK, Penny , CEURTER, Kevin J. , YAN, Hongfei
IPC分类号： H01L23/34 , H01L23/00 , H01L23/48 , H01L23/498
CPC分类号： H01L23/345 , H01L21/4853 , H01L21/4871 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0655 , H01L2223/6677 , H01L2224/0401 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/81908 , H01L2224/92125 , H01L2924/00014 , H01L2924/10253 , H01L2924/1432 , H01L2924/1434 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2224/45099 , H01L2924/00
摘要： Disclosed herein are integrated circuit (IC) package support structures, and related systems, devices, and methods. In some embodiments, an IC package support structure may include a first heater trace, and a second heater trace, wherein the second heater trace is not conductively coupled the first heater trace in the IC package support structure.
摘要翻译：这里公开了集成电路（IC）封装支撑结构以及相关的系统，装置和方法。在一些实施例中，IC封装支撑结构可以包括第一加热器迹线和第二加热器迹线，其中第二加热器迹线不导电地耦合到IC封装支撑结构中的第一加热器迹线。

88. 发明申请

WO2017052894A1 THERMAL MANAGEMENT FOR FLEXIBLE INTEGRATED CIRCUIT PACKAGES 审中-公开
标题翻译：柔性集成电路封装的热管理
公开(公告)号：WO2017052894A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048163
申请日：2016-08-23
申请人： INTEL CORPORATION
发明人： KUMAR, Siddarth , DHAVALESWARAPU, Hemanth K.
IPC分类号： H01L23/498 , H01L23/495 , H01L23/538
CPC分类号： H01L23/473 , H01L21/4882 , H01L23/145 , H01L23/5384 , H01L23/5387 , H01L25/0655 , H01L25/0657 , H01L2225/06548 , H01L2225/06589
摘要： Disclosed herein are systems and methods for thermal management of a flexible integrated circuit (IC) package. In some embodiments, a flexible IC package may include a flexible substrate material; a component disposed in the flexible substrate material; a channel disposed in the flexible substrate material forming a closed circuit and having a portion proximate to the component; electrodes disposed in the flexible substrate material and positioned at locations proximate to the channel, wherein the electrodes are coupled to an electrode controller to selectively cause one or more of the electrodes to generate an electric field; and an electrolytic fluid disposed in the channel. In some embodiments, a flexible IC package may be coupled to a wearable support structure. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了用于柔性集成电路（IC）封装的热管理的系统和方法。在一些实施例中，柔性IC封装可以包括柔性衬底材料; 设置在柔性基板材料中的部件; 通道，其设置在所述柔性基板材料中，形成闭合电路并且具有靠近所述部件的部分; 电极设置在柔性衬底材料中并且位于靠近通道的位置处，其中电极耦合到电极控制器以选择性地使一个或多个电极产生电场; 以及设置在通道中的电解液。在一些实施例中，柔性IC封装可以耦合到可穿戴支撑结构。可以公开和/或要求保护其他实施例。

89. 发明申请

WO2015147986A1 MULTINODE HUBS FOR TRUSTED COMPUTING 审中-公开
标题翻译：用于信用计算的MULTINODE HUBS
公开(公告)号：WO2015147986A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/013942
申请日：2015-01-30
申请人： INTEL CORPORATION
发明人： SWANSON, Robert C. , NEMIROFF, Daniel , ZIMMER, Vincent J. , BULUSU, Mallik , LINDSLEY, John R. , CONE, Robert W. , TRIVEDI, Malay , KWIDZINSKI, Piotr
IPC分类号： G06F12/02 , G06F13/16
CPC分类号： H04L63/10 , G06F3/0622 , G06F3/0637 , G06F3/0683 , G06F13/28 , G06F21/554 , G06F21/57 , G06F21/572
摘要： Embodiments of multinode hubs for trust operations are disclosed herein. In some embodiments, a multinode hub may include a plurality of memory regions, a trapping module, and a trusted platform module (TPM) component. Each memory region may be associated with and receive trust operation data from a coherent computing node. The trapping module may generate trap notifications in response to accesses to the plurality of memory regions by the associated coherent computing nodes. The trap notifications may indicate which of the plurality of memory locations has been accessed, and the TPM component may process the trust operation data in a memory region indicated by a trap notification. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了用于信任操作的多节点集线器的实施例。在一些实施例中，多节点集线器可以包括多个存储器区域，陷阱模块和可信平台模块（TPM）组件。每个存储器区域可以与相干计算节点相关联并接收来自相干计算节点的信任操作数据。捕获模块可以响应于相关联的相干计算节点对多个存储器区域的访问而产生陷阱通知。陷阱通知可以指示已经访问了多个存储器位置中的哪一个，并且TPM组件可以处理由陷阱通知指示的存储器区域中的信任操作数据。可以公开和/或要求保护其他实施例。

90. 发明申请

WO2015142322A1 SEMICONDUCTOR ASSEMBLIES WITH FLEXIBLE SUBSTRATES 审中-公开
标题翻译：具有柔性基板的半导体组件
公开(公告)号：WO2015142322A1
公开(公告)日：2015-09-24
申请号：PCT/US2014/031094
申请日：2014-03-18
申请人： INTEL CORPORATION , MUKHERJEE, Niloy , DOYLE, Brian, S. , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , PILLARISETTY, Ravi , THEN, Han Wui , RAO, Valluri, R. , CHAU, Robert, S.
发明人： MUKHERJEE, Niloy , DOYLE, Brian, S. , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , PILLARISETTY, Ravi , THEN, Han Wui , RAO, Valluri, R. , CHAU, Robert, S.
IPC分类号： H01L29/04 , H01L21/763
CPC分类号： H01L21/02513 , H01L21/02164 , H01L21/02178 , H01L21/02186 , H01L21/0228 , H01L21/02282 , H01L21/02422 , H01L21/02428 , H01L21/02488 , H01L21/02521 , H01L21/02532 , H01L21/02538 , H01L21/02549 , H01L21/02551 , H01L21/02595 , H01L21/02631 , H01L21/02675 , H01L21/763 , H01L27/1218 , H01L27/1225 , H01L29/78603 , H01L29/78681
摘要： Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了半导体组件的实施例以及相关的集成电路器件和技术。在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料和布置在柔性衬底和多晶半导体材料之间和之后的多晶电介质。多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。可以公开和/或要求保护其他实施例。

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