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    • 72. 发明申请
    • METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 制造半导体集成电路器件的方法
    • WO1998001903A1
    • 1998-01-15
    • PCT/JP1996001901
    • 1996-07-09
    • HITACHI, LTD.IKOTA, MasamiSUGIMOTO, Aritoshi
    • HITACHI, LTD.
    • H01L21/66
    • B82Y10/00B82Y40/00G01N21/9501G01N21/956G03F1/84G03F7/70425G03F7/70433G03F7/70616G03F7/7065H01J37/3174
    • A method of manufacturing a semiconductor integrated circuit device, in which pattern on photomasks are transferred to a semiconductor wafer, and particularly techniques are employed for using control data, production condition data and inspection data in common in different production steps. A photomask is produced at a photomask production step by electron beam lithography. The same coordinate system of the pattern data used at the photomask production step are used in inspection/correction steps. The mask pattern of the photomask is transferred to the wafer by a step-and-repeat system. In this instance, the step movement is depending on the coordinate system of the pattern data. The wafer so exposed is then developed and etched to form repeats of reduced patterns on it, that is, this wafer pattern is composed of the reduced pattern produced by a step-and-repeat technique according to the coordinate system of the pattern data. The coordinate system of the pattern data is used to inspect the patterned wafers on a wafer tester. If a defect is found on a wafer, a detailed inspection of the corresponding photomask is carried out in a photomask inspection/correction step based on the results of the patterned wafer inspection step. Since the inspection result data comprises the coordinate system of the pattern data, it can be utilized as the data for the detailed inspection.
    • 制造将光掩模上的图案转印到半导体晶片的半导体集成电路器件的制造方法,特别是在不同的制造步骤中共同使用控制数据,生产条件数据和检查数据的技术。 通过电子束光刻在光掩模制造步骤中制造光掩模。 在光掩模生产步骤中使用的图案数据的相同坐标系用于检查/校正步骤。 通过步进重复系统将光掩模的掩模图案转移到晶片。 在这种情况下,步进运动取决于模式数据的坐标系。 然后,如此曝光的晶片被显影和蚀刻以形成其上减少图案的重复,即,该晶片图案由根据图案数据的坐标系的步进重复技术产生的缩小图案组成。 图案数据的坐标系用于检查晶片测试仪上的图案化晶片。 如果在晶片上发现缺陷,则基于图案化晶片检查步骤的结果,在光掩模检查/校正步骤中进行相应的光掩模的详细检查。 由于检查结果数据包括图案数据的坐标系,因此可以用作详细检查的数据。
    • 74. 发明申请
    • ELECTRON BEAM EXPOSURE METHOD
    • 电子束曝光方法
    • WO1993009561A1
    • 1993-05-13
    • PCT/US1992000770
    • 1992-01-29
    • INTERNATIONAL BUSINESS MACHINES CORPORATION
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONDICK, Gregory, James
    • H01J37/302
    • H01J37/3174B82Y10/00B82Y40/00H01J37/3026H01J2237/31761H01J2237/31769
    • A more efficient method of macro placement and graying for electron beam (e-beam) lithography. The e-beam field is divided into smaller subfields. Repetitious shapes or collections of shapes which are repetitious are represented by macros. Some shapes span or are intersected by subfield boundaries. After the shapes are converted to fill rectangles and the fill rectangles are proximity corrected, the macro containing the proximity corrected fill rectangles is grayed and placed without being unnested. First, the Macro Organization Step, the macro's fill rectangles are sorted. Tall-narrow macros are sorted top to bottom then left to right, short-wide macros are sorted left to right then top to bottom. After the sort, chains of rectangles are created and a shadow is generated for the macro and for each chain. Next, the Macro Placement and Graying Step, a determination is made of whether and where macro graying will be required. The macro shadow is transformed into subfield coordinates and a determination is made of whether the transformed shadow intersects with (spans) a subfield boundary. If the macro's shadow touches more than one subfield (spans a subfield boundary), then the macro's chain shadows are examined to deternine if any chain spans the boundary. Graying is done on any spanning chain. Gray-spliced rectangles and single rectangles are placed in the pattern buffer. Partial macro read commands are placed in the pattern buffer for chains or partial chains resulting from gray-splicing.
    • 80. 发明申请
    • METHOD FOR DETERMINING THE PARAMETERS OF AN IC MANUFACTURING PROCESS MODEL
    • 用于确定IC制造工艺模型参数的方法
    • WO2016020264A1
    • 2016-02-11
    • PCT/EP2015/067535
    • 2015-07-30
    • ASELTA NANOGRAPHICS
    • SAIB, MohamedSCHIAVONE, PatrickFIGUEIRO, Thiago
    • H01J37/317G03F7/20G03F1/36
    • G03F7/70441G03F1/36H01J37/3026H01J37/3174H01J2237/31769H01J2237/31796
    • According to the invention, an IC manufacturing model is disclosed, wherein input variables and an output variable are measured using a calibration set of patterns. The model can or not include a PSF. The output variable may be a dimensional bias between printed patterns and target patterns or simulated patterns. It can also be a Threshold To Meet Experiments (TTME). The input variables may be defined by a metric which uses kernel functions, preferably with a deformation function which includes a shift angle and a convolution procedure. A functional or associative relationship between the input variables and the output variable is defined. Preferably this definition includes normalization steps and interpolation steps. Advantageously, the interpolation step is of the kriging type. The invention achieves a much more accurate modeling of IC manufacturing, simulation or inspection processes.
    • 根据本发明,公开了一种IC制造模型,其中使用校准图案集来测量输入变量和输出变量。 该模型可以或不包括PSF。 输出变量可以是印刷图案和目标图案或模拟图案之间的尺寸偏差。 它也可以是满足实验的门槛(TTME)。 输入变量可以由使用内核函数的度量定义,优选地具有包括移​​位角和卷积过程的变形函数。 定义输入变量和输出变量之间的函数关系或关联关系。 优选地,该定义包括归一化步骤和内插步骤。 有利地,内插步骤是克里金型。 本发明实现了对IC制造,仿真或检验过程的更准确的建模。