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51. 发明申请

WO2013058745A1 METHODS AND SYSTEMS FOR MANAGING SYNONYMS IN VIRTUALLY INDEXED PHYSICALLY TAGGED CACHES 审中-公开
标题翻译：用于管理虚拟索引物理标签快照中的同步的方法和系统
公开(公告)号：WO2013058745A1
公开(公告)日：2013-04-25
申请号：PCT/US2011/056757
申请日：2011-10-18
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0822 , G06F12/0855 , G06F12/1054 , G06F12/1063 , G06F2212/283 , G06F2212/621
摘要： Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.
摘要翻译：公开了用于管理VIPT高速缓存中的同义词的方法和系统。一种方法包括使用目录跟踪复制的高速缓存行，检查与加载请求相关联的虚拟地址的指定位，并且基于状态确定其状态并在目录的多个部分之一中进行条目的被检查的虚拟地址的指定位。该方法还包括更新与存储在复制的高速缓存的第一索引中的虚拟地址相关联的高速缓存行中的一个并且使另一个无效，以及与虚拟地址的同义词相关联的高速缓存行其被存储在复制的高速缓存的第二索引处，当接收到更新与虚拟地址相关联的物理地址的请求时。

52. 发明申请

WO2012119430A3 ADDRESS ACCESSING METHOD, DEVICE AND SYSTEM 审中-公开
标题翻译：地址访问方法，设备和系统
公开(公告)号：WO2012119430A3
公开(公告)日：2012-11-01
申请号：PCT/CN2011079172
申请日：2011-08-31
申请人： HUAWEI TECH CO LTD , FAN CHUNLEI
发明人： FAN CHUNLEI
IPC分类号： G06F12/08
CPC分类号： G06F12/0855
摘要： Disclosed are an address accessing method and device, relating to the technical field of cache management, solving the queue head blockage caused by order preservation on read/write request with the same address. The present invention includes: receiving a read/write request for accessing a first address; judging whether or not there is any read/write request accessing the first address; if there is a read/write request accessing the first address, then obtaining the access matching value corresponding to the first address recorded in an address access control module, and sending the access matching value and the read/write request to a read/write operating module; if there is no read/write request accessing the first address, then allocating an access matching value for the access request for the first address, and sending the matching value and the read/write request to the read/write operating module. The embodiments of the present invention are mainly used in the processing of address access control.
摘要翻译：公开了一种涉及高速缓存管理技术领域的地址访问方法和设备，解决了具有相同地址的读/写请求时由命令保存引起的队列头阻塞。本发明包括：接收访问第一地址的读/写请求; 判断是否存在访问第一地址的读/写请求; 如果存在访问第一地址的读/写请求，则获得与记录在地址访问控制模块中的第一地址相对应的访问匹配值，并将访问匹配值和读/写请求发送到读/写操作模块; 如果没有访问第一地址的读/写请求，则为第一地址的访问请求分配访问匹配值，并将匹配值和读/写请求发送到读/写操作模块。本发明的实施例主要用于地址访问控制的处理。

53. 发明申请

WO2012024053A2 METHOD AND SYSTEM OF HANDLING NON-ALIGNED MEMORY ACCESSES 审中-公开
标题翻译：处理非对准存储器访问的方法和系统
公开(公告)号：WO2012024053A2
公开(公告)日：2012-02-23
申请号：PCT/US2011044977
申请日：2011-07-22
申请人： INTEL CORP , SHEAFFER GAD S
发明人： SHEAFFER GAD S
IPC分类号： G06F12/08
CPC分类号： G06F12/0855
摘要： A method and system to facilitate full throughput operation of cache memory line split accesses in a device. By facilitating full throughput operation of cache memory line split accesses in the device, the device minimizes the performance and throughput loss associated with the handling of non-aligned cache memory accesses that cross two or more cache memory lines and/or page memory boundaries in one embodiment of the invention. When the device receives a non-aligned cache memory access request, the merge logic combines or merges the incoming data of a particular cache memory line from a data cache memory with the stored data of the preceding cache memory line of the particular cache memory line.
摘要翻译：一种促进设备中高速缓存存储器线路拆分访问的全吞吐量操作的方法和系统。通过促进设备中高速缓存存储器线路拆分访问的完全吞吐量操作，该设备最小化与处理跨越两个或更多个高速缓冲存储器行和/或一个存储器边界的一个或多个高速缓冲存储器行和/或第本发明的实施例。当设备接收到不对齐的高速缓冲存储器访问请求时，合并逻辑将来自数据高速缓冲存储器的特定高速缓冲存储器行的输入数据与特定高速缓存存储器线的先前高速缓冲存储器行的存储数据组合或合并。

54. 发明申请

WO2006135590A2 METHOD AND APPARATUS FOR MANAGING INSTRUCTION FLUSHING IN A MICROPROCESSOR'S INSTRUCTION PIPELINE 审中-公开
标题翻译：用于管理微处理器指令管道中的指导性冲洗的方法和装置
公开(公告)号：WO2006135590A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/021617
申请日：2006-06-02
申请人： QUALCOMM INCORPORATED , MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： MCILVAINE, Michael Scott , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译：在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地从指令流水线中刷新指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新。因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令，这被标记为依赖于不正确的分支预测。

55. 发明申请

WO2004046931A1 メモリ制御装置およびストアバイパス制御方法审中-公开
标题翻译：存储控制装置和存储旁路控制方法
公开(公告)号：WO2004046931A1
公开(公告)日：2004-06-03
申请号：PCT/JP2002/012136
申请日：2002-11-20
申请人：富士通株式会社 , 桜井康智
发明人：桜井康智
IPC分类号： G06F12/08
CPC分类号： G06F9/3826 , G06F9/3834 , G06F12/0855
摘要： A memory control device comprises a cache access control unit (12) which reads data D1 corresponding to the address from a cache memory (13) according to an access request (a store access) from a CPU (11), and a merge unit (101) for merging the data D2 and to be stored and fed from the CPU (11) with data D1 and storing the merged result as data D3 in a store buffer (19). When an access request (a load access) corresponding to the same address is made from the CPU (11) before data D3 is stored in the cache memory (13), data D3 is loaded on the CPU (11) from the store buffer (19).
摘要翻译：存储器控制装置包括：高速缓存存取控制单元，其根据来自CPU（11）的访问请求（存储访问）从高速缓冲存储器读取与地址对应的数据D1;合并单元， 101），用于合并数据D2并由CPU（11）存储和馈送数据D1，并将合并结果作为数据D3存储在存储缓冲器（19）中。当在数据D3存储在高速缓冲存储器（13）中之前从CPU（11）获得对应于相同地址的访问请求（加载访问）时，数据D3从存储缓冲器（ 19）。

56. 发明申请

WO2003001369A2 METHOD AND APPARATUS FOR FACILITATING SPECULATIVE STORES IN A MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：用于在多处理器系统中促进分析存储的方法和装置
公开(公告)号：WO2003001369A2
公开(公告)日：2003-01-03
申请号：PCT/US2002/022157
申请日：2002-06-26
申请人： SUN MICROSYSTEMS, INC.
发明人： TREMBLAY, Marc , CHAUDHRY, Shailender
IPC分类号： G06F9/38
CPC分类号： G06F9/3834 , G06F9/383 , G06F9/3842 , G06F9/3861 , G06F12/0811 , G06F12/0815 , G06F12/0855 , G06F2212/507
摘要： One embodiment of the present invention provides a system for facilitating speculative store operations in a multiprocessor system. This system operates by maintaining a record of speculative store operations that are in process at an L2 cache in the multiprocessor system, wherein a speculative store operation is a store operation that is speculatively executed before a preceding store operation has returned. Upon receiving a load operation at the L2 cache from an L1 cache, the system examines the record of speculative store operations to determine if there exists a matching speculative store operation that is directed to the same location that the load operation is directed to. If so, the system ensures that the load operation takes place after the matching speculative store operation completes.
摘要翻译：本发明的一个实施例提供一种用于促进多处理器系统中的推测存储操作的系统。该系统通过维持在多处理器系统中的L2高速缓存处理中的推测存储操作的记录来进行操作，其中推测存储操作是在先前的存储操作返回之前被推测地执行的存储操作。在从L1高速缓存接收到L2高速缓存的加载操作时，系统检查推测存储操作的记录，以确定是否存在针对加载操作指向的相同位置的匹配推测存储操作。如果是这样，系统确保在匹配推测存储操作完成后进行加载操作。

57. 发明申请

WO01074134A3 SYSTEM HAVING A CONFIGURABLE CACHE/SRAM MEMORY 审中-公开
标题翻译：具有可配置缓存/ SRAM存储器的系统
公开(公告)号：WO01074134A3
公开(公告)日：2002-05-23
申请号：PCT/US2001/010299
申请日：2001-03-30
IPC分类号： G06F12/08 , G06F13/16
CPC分类号： G06F12/0855 , G06F12/0893 , G06F13/16
摘要： An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.
摘要翻译：公开了一种具有核心处理器和存储器系统的设备。核心处理器包括至少一个数据端口。存储器系统以这样的方式连接，以便通过数据端口提供基本上同时的数据访问。存储器系统可以由用户配置来提供适当的存储器模型。

58. 发明申请

WO1993019424A1 SYSTEM AND METHOD FOR SUPPORTING A MULTIPLE WIDTH MEMORY SUBSYSTEM 审中-公开
标题翻译：用于支持多个宽度存储器子系统的系统和方法
公开(公告)号：WO1993019424A1
公开(公告)日：1993-09-30
申请号：PCT/JP1993000317
申请日：1993-03-17
申请人： SEIKO EPSON CORPORATION
发明人： SEIKO EPSON CORPORATION , LENTZ, Derek, J. , TANG, Cheng-Long
IPC分类号： G06F13/40
CPC分类号： G06F13/18 , G06F12/0855 , G06F13/4018
摘要： The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. Selecting a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.
摘要翻译：本发明提供一种提供对双宽度存储器总线的访问的存储器系统接口设计。具体来说，子系统和方法提供与32位或64位总线的接口。 32位总线将用于低端产品，64位总线将用于高端产品。存储器控制单元（MCU）同时支持32位和64位模式。选择32位或64位内存子系统可为用户提供更多的空间来调整系统成本和性能。

59. 发明申请

WO2015183467A1 METHOD AND APPARATUS FOR CACHE ACCESS MODE SELECTION 审中-公开
标题翻译：缓存访问模式选择的方法和设备
公开(公告)号：WO2015183467A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/028720
申请日：2015-05-01
申请人： QUALCOMM INCORPORATED
发明人： VENKUMAHANTI, Suresh Kumar , SHANNON, Stephen Robert
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F12/0884 , G06F9/30189 , G06F9/3802 , G06F9/3824 , G06F9/3851 , G06F12/0811 , G06F12/0846 , G06F12/0855 , G06F12/0857 , G06F12/0864 , G06F12/0877 , G06F2212/1028 , G06F2212/283 , G06F2212/6012 , G06F2212/603 , Y02D10/13
摘要： A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
摘要翻译：特定方法包括基于存储在发布队列中的指令数量，执行单元的活动线程的数量或两者来选择第一高速缓存访问模式和第二高速缓存访问模式。该方法还包括执行第一高速缓存访问。当选择第一高速缓存访问模式时，执行第一高速缓存访问包括执行标签访问并且在执行标签访问之后执行数据阵列访问。当选择第二高速缓存访问模式时，执行第一高速缓存访问包括与数据阵列访问并行地执行标签访问。

60. 发明申请

WO2015061014A1 SPLIT WRITE OPERATION FOR RESISTIVE MEMORY CACHE 审中-公开
标题翻译：电阻式存储器高速缓存的分离写操作
公开(公告)号：WO2015061014A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/058668
申请日：2014-10-01
申请人： QUALCOMM INCORPORATED
发明人： DONG, Xiangyu , ZHU, Xiaochun , SUH, Jungwon
IPC分类号： G11C7/10 , G06F12/08 , G11C11/16
CPC分类号： G06F12/0802 , G06F12/08 , G06F12/0855 , G06F12/0864 , G06F2212/1016 , G06F2212/22 , G06F2212/222 , G06F2212/60 , G11C7/1015 , G11C7/1039 , G11C7/1084 , G11C11/165 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C13/0002 , G11C2207/2245 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.
摘要翻译：一种读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。

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