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1. 发明申请

WO2014150941A1 A METHOD FOR EXECUTING BLOCKS OF INSTRUCTIONS USING A MICROPROCESSOR ARCHITECTURE HAVING A REGISTER VIEW, SOURCE VIEW, INSTRUCTION VIEW, AND A PLURALITY OF REGISTER TEMPLATES 审中-公开
标题翻译：使用具有寄存器视图，源视图，指令视图和多个寄存器模板的微处理器架构来执行指令块的方法
公开(公告)号：WO2014150941A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024608
申请日：2014-03-12
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/30 , G06F9/06
CPC分类号： G06F9/30098 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3863 , G06F9/5005
摘要： A method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; using a register view data structure, wherein the register view data structure stores destinations corresponding to the instruction blocks; using a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks; and using an instruction view data structure, wherein the instruction view data structure stores instructions corresponding to the instruction blocks.
摘要翻译：一种使用具有寄存器视图，源视图，指令视图和多个寄存器模板的微处理器架构来执行指令块的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 使用多个寄存器模板来通过用对应于指令块的块号填充寄存器模板来跟踪指令目的地和指令源，其中对应于指令块的块号指示指令块之间的相互依赖关系; 使用注册视图数据结构，其中所述注册视图数据结构存储与所述指令块相对应的目的地; 使用源视图数据结构，其中所述源视图数据结构存储与所述指令块相对应的源; 并且使用指令视图数据结构，其中指令视图数据结构存储与指令块相对应的指令。

2. 发明申请

WO2014022115A1 SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE 审中-公开
标题翻译：用于在单周期中支持高速缓存的多重负载接入的系统和方法
公开(公告)号：WO2014022115A1
公开(公告)日：2014-02-06
申请号：PCT/US2013/051128
申请日：2013-07-18
申请人： SOFT MACHINES, INC. , AVUDAIYAPPAN, Karthikeyan , ABDALLAH, Mohammad
发明人： AVUDAIYAPPAN, Karthikeyan , ABDALLAH, Mohammad
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0846
摘要： A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory.
摘要翻译：公开了一种用于支持多个负载访问的方法。访问多个访问数据高速缓存的请求，并且作为响应，访问维护数据高速缓存中的每个条目的多个标签副本的标签存储器。识别符合个别请求的标签。基于与各个请求对应的标签访问数据高速缓存。多个访问多个块的相同块的请求导致在与标签存储器的访问相同的时钟周期中执行的访问仲裁。

3. 发明申请

WO2013077872A1 A MICROPROCESSOR ACCELERATED CODE OPTIMIZER AND DEPENDENCY REORDERING METHOD 审中-公开
标题翻译：微处理器加速代码优化器和依赖性方法
公开(公告)号：WO2013077872A1
公开(公告)日：2013-05-30
申请号：PCT/US2011/061940
申请日：2011-11-22
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/305 , G06F9/30 , G06F9/06
CPC分类号： G06F9/30145 , G06F9/30098 , G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A dependency reordering method. The method includes accessing an input sequence of instructions, initializing three registers, and loading instruction numbers into a first register. The method further includes loading destination register numbers into a second register, broadcasting values from the first register to a position in a third register in accordance with a position number in the second register, overwriting positions in the third register in accordance with position numbers in the second register, and using information in the third register to populate a dependency matrix for grouping dependent instructions from the sequence of instructions.
摘要翻译：依赖关系重新排序方法。该方法包括访问输入的指令序列，初始化三个寄存器，以及将指令编号加载到第一寄存器中。该方法还包括将目的地寄存器号码加载到第二寄存器中，根据第二寄存器中的位置号从第一寄存器广播值到第三寄存器中的位置，根据第二寄存器中的位置号重写第三寄存器中的位置第二寄存器，以及使用第三寄存器中的信息来填充依赖矩阵，用于从指令序列中分组相关指令。

4. 发明申请

WO2013058745A1 METHODS AND SYSTEMS FOR MANAGING SYNONYMS IN VIRTUALLY INDEXED PHYSICALLY TAGGED CACHES 审中-公开
标题翻译：用于管理虚拟索引物理标签快照中的同步的方法和系统
公开(公告)号：WO2013058745A1
公开(公告)日：2013-04-25
申请号：PCT/US2011/056757
申请日：2011-10-18
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833 , G06F12/0811 , G06F12/0822 , G06F12/0855 , G06F12/1054 , G06F12/1063 , G06F2212/283 , G06F2212/621
摘要： Methods and systems for managing synonyms in VIPT caches are disclosed. A method includes tracking lines of a copied cache using a directory, examining a specified bit of a virtual address that is associated with a load request and determining its status and making an entry in one of a plurality of parts of the directory based on the status of the specified bit of the virtual address that is examined. The method further includes updating one of, and invalidating the other of, a cache line that is associated with the virtual address that is stored in a first index of the copied cache, and a cache line that is associated with a synonym of the virtual address that is stored at a second index of the copied cache, upon receiving a request to update a physical address associated with the virtual address.
摘要翻译：公开了用于管理VIPT高速缓存中的同义词的方法和系统。一种方法包括使用目录跟踪复制的高速缓存行，检查与加载请求相关联的虚拟地址的指定位，并且基于状态确定其状态并在目录的多个部分之一中进行条目的被检查的虚拟地址的指定位。该方法还包括更新与存储在复制的高速缓存的第一索引中的虚拟地址相关联的高速缓存行中的一个并且使另一个无效，以及与虚拟地址的同义词相关联的高速缓存行其被存储在复制的高速缓存的第二索引处，当接收到更新与虚拟地址相关联的物理地址的请求时。

5. 发明申请

WO2012162189A1 AN INTERCONNECT STRUCTURE TO SUPPORT THE EXECUTION OF INSTRUCTION SEQUENCES BY A PLURALITY OF ENGINES 审中-公开
标题翻译：支持大量引擎执行指令序列的互连结构
公开(公告)号：WO2012162189A1
公开(公告)日：2012-11-29
申请号：PCT/US2012/038713
申请日：2012-05-18
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F13/14 , G06F13/38 , G06F9/06
CPC分类号： G06F9/5077 , G06F9/3012 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3851 , G06F9/3891 , G06F9/46 , G06F9/4881 , G06F9/52 , G06F13/4068 , G06F15/80
摘要： A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.
摘要翻译：全球互连系统。全局互连系统包括具有用于支持多个代码序列的执行的数据的多个资源和用于实现多个代码序列的执行的多个引擎。多个资源消耗者在多个发动机的每一个内。全局互连结构耦合到多个资源使用者，并耦合到多个资源，以实现多个代码序列的数据访问和执行，其中资源使用者通过全局互连结构的每周期利用来访问资源。

6. 发明申请

WO2012135050A2 MEMORY FRAGMENTS FOR SUPPORTING CODE BLOCK EXECUTION BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES 审中-公开
标题翻译：使用可分割引擎的虚拟核心支持代码块执行的内存碎片
公开(公告)号：WO2012135050A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/030409
申请日：2012-03-23
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/06 , G06F9/30 , G06F12/08 , G06F15/76
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30189 , G06F9/3834 , G06F9/3838 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3889 , G06F9/5027 , G06F12/0875 , G06F2209/507 , G06F2212/452 , Y02D10/22
摘要： A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.
摘要翻译：用于使用用于处理器的多个存储器片段来执行指令的系统
。该系统包括用于接收传入指令序列的全局前端调度器，其中全局前端调度器将传入指令序列分割为多个指令代码块并且生成描述代码块指令之间的相互依赖性的多个继承向量。该系统还包括处理器的多个虚拟核心，其被耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分割引擎的相应的资源子集，其中代码块通过使用根据虚拟核心模式并根据相应的继承向量来执行可分区引擎。多个存储器片段被耦合到可分区引擎以提供数据存储。

7. 发明申请

WO2012103359A2 HARDWARE ACCELERATION COMPONENTS FOR TRANSLATING GUEST INSTRUCTIONS TO NATIVE INSTRUCTIONS 审中-公开
标题翻译：硬件加速组件，用于将客户指令翻译为本地指令
公开(公告)号：WO2012103359A2
公开(公告)日：2012-08-02
申请号：PCT/US2012/022760
申请日：2012-01-26
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F1/00 , G06F9/30 , G06F9/38 , G06F15/76
CPC分类号： G06F9/30174 , G06F9/30018 , G06F9/30021 , G06F9/30029 , G06F9/30098 , G06F9/30189 , G06F9/3802 , G06F9/3814 , G06F9/3842 , G06F9/3844 , G06F9/3857 , G06F9/3861 , G06F9/3863 , G06F9/3867 , G06F9/3879 , G06F9/45516 , G06F12/0875 , G06F15/8007 , G06F2212/452
摘要： A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.
摘要翻译：
基于硬件的翻译加速器。该硬件包括用于访问访客指令的访客提取逻辑组件; 耦合到所述访客提取逻辑组件的访客提取缓冲器和用于将访客指令组装成访客指令块的分支预测组件; 以及耦合到访客提取缓冲器的转换表，用于将访客指令块翻译成对应的本地转换块。硬件进一步包括耦合到转换表以存储对应的本地转换块的本地高速缓存以及耦合到本地高速缓存的用于存储客户指令块到对应本地转换块的映射的转换后备缓冲器，其中在随后的请求访客指令时，对转换后备缓冲器进行索引以确定是否发生了命中，其中该映射指示访客指令在本地缓存中具有对应的经转换的本机指令。

8. 发明申请

WO2012103209A3 GUEST INSTRUCTION TO NATIVE INSTRUCTION RANGE BASED MAPPING USING A CONVERSION LOOK ASIDE BUFFER OF A PROCESSOR 审中-公开
公开(公告)号：WO2012103209A3
公开(公告)日：2012-08-02
申请号：PCT/US2012/022538
申请日：2012-01-25
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
摘要： A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions, and assembling the plurality of guest instructions into a guest instruction block. The guest instruction block is converted into a corresponding native conversion block. The native conversion block is stored into a native cache. A mapping of the guest instruction block to corresponding native conversion block is stored in a conversion look aside buffer. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates whether the guest instruction has a corresponding converted native instruction in the native cache. The converted native instruction is forwarded for execution in response to the hit.

9. 发明申请

WO2014151722A1 METHOD AND APPARATUS FOR SORTING ELEMENTS IN HARDWARE STRUCTURES 审中-公开
标题翻译：用于在硬件结构中分配元素的方法和装置
公开(公告)号：WO2014151722A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/026312
申请日：2014-03-13
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad , SINGH, Mandeep
发明人： ABDALLAH, Mohammad , SINGH, Mandeep
IPC分类号： G06F9/46 , G06F9/305 , G06F9/38
CPC分类号： G06F9/3855 , G06F9/3834 , G06F9/3857
摘要： A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.
摘要翻译：公开了一种在硬件结构中对元件进行排序的方法。该方法包括从预定范围内的无序输入队列（UIQ）中选择多个元素以响应于找到预定范围的至少一个最高有效位与相关标识符的相应位的匹配多个元素。该方法还包括将多个元件中的每一个呈现给相应的多路复用器。此外，所述方法包括：响应于找到与所述多个元素中的每一个相关联的相应标识符的至少一个最低有效位与所述有序队列的端口号之间的匹配来产生用于使能多路复用器的选择信号。最后，该方法包括将与所选择的元素标识符相关联的分组从所启用的多路复用器转发到有序队列的匹配端口号。

10. 发明申请

WO2014151691A1 METHOD AND APPARATUS FOR GUEST RETURN ADDRESS STACK EMULATION SUPPORTING SPECULATION 审中-公开
标题翻译：用于返回地址堆栈模拟支持参数的方法和装置
公开(公告)号：WO2014151691A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/026252
申请日：2014-03-13
申请人： SOFT MACHINES, INC. , ABDALLAH, Mohammad
发明人： ABDALLAH, Mohammad
IPC分类号： G06F9/42 , G06F9/455 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3017
摘要： A microprocessor implemented method for maintaining a guest return address stack in an out-of- order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS.
摘要翻译：公开了一种用于在无序微处理器管线中维护客户返回地址堆栈的微处理器实现的方法。该方法包括将访客地址空间中的多个指令映射到本机地址空间中的对应的多个指令中。对于在执行期间获取的本地地址空间中的每个功能调用指令，该方法还包括执行以下操作：（a）响应于函数调用将当前条目推送到客户返回地址堆栈（GRAS），其中GRAS保持在所述流水线的获取阶段，并且其中当前条目包括关于访客目标返回地址和与所述功能调用相关联的对应本地目标返回地址两者的信息; （b）响应处理退货指示，从GRAS弹出当前条目; 和（c）从GRAS弹出后从当前条目中的本地目标返回地址获取指令。

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