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41. 发明申请

WO2013095846A1 MITIGATING VARIATIONS ARISING FROM SIMULTANEOUS MULTI-STATE SENSING 审中-公开
标题翻译：缓解同时多状态感觉造成的变化
公开(公告)号：WO2013095846A1
公开(公告)日：2013-06-27
申请号：PCT/US2012/065948
申请日：2012-11-19
申请人： SANDISK TECHNOLOGIES, INC. , SHARON, Eran
发明人： SHARON, Eran
IPC分类号： G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G06F11/1072
摘要： Methods and devices for mitigating sensing variations that may arise from simultaneous multi-threshold (SMT) sensing are provided. During SMT sensing, two or more different bias conditions may be used to simultaneously sense two different threshold voltages. However, there may be variances in the threshold voltage shift of memory cells when read with a different bias condition than was used to verify. In one embodiment each programmed state is read using both (or all) bias conditions that were used during SMT verify. In other words, two (or more) different sense operations are used to read each memory cell. The data from these different sense operations may be used to compute initialization values (e.g., LLRs, LRs, probabilities) for an ECC decoder. In one embodiment, this technique is only performed when a normal read fails.
摘要翻译：提供了用于减轻可能由同步多阈值（SMT）感测引起的感测变化的方法和设备。在SMT感测期间，可以使用两个或多个不同的偏置条件来同时感测两个不同的阈值电压。然而，当以不同于用于验证的偏置条件读取时，存储器单元的阈值电压偏移可能存在差异。在一个实施例中，使用在SMT验证期间使用的（或全部）偏置条件来读取每个编程状态。换句话说，使用两个（或多个）不同的感测操作来读取每个存储器单元。可以使用来自这些不同感测操作的数据来计算用于ECC解码器的初始化值（例如，LLR，LR，概率）。在一个实施例中，仅当正常读取失败时才执行该技术。

42. 发明申请

WO2013016397A2 POST-WRITE READ IN NON-VOLATILE MEMORIES USING COMPARISON OF DATA AS WRITTEN IN BINARY AND MULTI-STATE FORMATS 审中-公开
标题翻译：在非易失性存储器中使用双向和多态格式中的数据进行比较读写
公开(公告)号：WO2013016397A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/048087
申请日：2012-07-25
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C16/34 , G11C11/56 , G06F11/10
CPC分类号： G11C16/3459 , G06F11/1072 , G11C11/5628 , G11C16/3481 , G11C2211/5641
摘要： Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.
摘要翻译：介绍了写入后读取技术。在示例性实施例中，主数据最初以二进制形式写入非易失性存储器，例如非易失性二进制高速缓存。随后将其从二进制部分写入存储器的多状态非易失性部分。在以多状态格式写入后，可以在二进制部分的源页面中检查来自多状态块的数据页面，以验证多状态写入的质量。该过程可以在存储器设备本身上执行，而不将页面传送到控制器。

43. 发明申请

WO2013016168A2 SYSTEMS AND METHODS OF STORING DATA 审中-公开
标题翻译：存储数据的系统和方法
公开(公告)号：WO2013016168A2
公开(公告)日：2013-01-31
申请号：PCT/US2012/047545
申请日：2012-07-20
申请人： SANDISK TECHNOLOGIES INC. , SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon , LASSER, Menahem
IPC分类号： G06F11/10
CPC分类号： G11C7/1006 , G06F11/1044 , G06F11/1068 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C29/78 , G11C2211/5641
摘要： Systems and methods of storing data are disclosed.
摘要翻译：公开了存储数据的系统和方法。

44. 发明申请

WO2009156883A1 OVERCOMING LDPC TRAPPING SETS BY DECODER RESET 审中-公开
标题翻译：通过解码器复位来覆盖LDPC陷波器
公开(公告)号：WO2009156883A1
公开(公告)日：2009-12-30
申请号：PCT/IB2009/052204
申请日：2009-05-26
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon
IPC分类号： H03M13/11
CPC分类号： H03M13/1131 , H03M13/1111 , H03M13/2951 , H03M13/3738
摘要： To decode, in a plurality of iterations, a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N-K check nodes of a graph. If the decoding has failed to converge according to a predetermined failure criterion and if the codeword bit estimates satisfy a criterion symptomatic of the graph including a trapping set, at least a portion of the messages are reset before continuing the iterations. Alternatively, if the decoding fails to converge according to a predetermined failure criterion, at least a portion of the messages that are sent from the bit nodes are truncated before continuing the iterations.
摘要翻译：为了在多个迭代中将从信道导入的代码字解码为将K个信息比特编码为N> K个码字比特的码字，通过在N个比特节点和NK个查询节点之间交换消息来更新码字比特的估计的图表。如果解码未能根据预定的故障标准进行收敛，并且如果码字比特估计满足包括陷印集的图形的症状的标准，则在继续迭代之前至少部分消息被重置。或者，如果解码根据预定的故障准则不能收敛，则在继续迭代之前，将从比特节点发送的消息的至少一部分截断。

45. 发明申请

WO2009040784A1 POST-FACTO CORRECTION FOR CROSS COUPLING IN A FLASH MEMORY 审中-公开
标题翻译：用于闪存存储器中的交叉耦合的后验证校正
公开(公告)号：WO2009040784A1
公开(公告)日：2009-04-02
申请号：PCT/IL2008/000855
申请日：2008-06-23
申请人： SANDISC IL Ltd. , ALROD, Idan , SHARON, Eran
发明人： ALROD, Idan , SHARON, Eran
IPC分类号： G11C16/26 , G11C16/34 , G11C11/56 , G06F11/10
CPC分类号： G11C11/5642 , G11C16/3418 , G11C2211/5634
摘要： A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.
摘要翻译：一种使用包括多个单元（例如闪存单元）的存储器来存储和读取数据的方法，使得通过将单元的物理参数（例如阈值电压）的相应值设置为指示来存储在单元中的数据的数据，并且通过测量这些值从单元读取数据。读取其中一个单元及其邻居。存储在单元中的数据基于测量以及相邻的干扰读数的相应范围来估计。优选地，该方法还包括例如基于测量本身来确定邻近者对其进行干扰的相应范围。

46. 发明申请

WO2008142683A2 MEMORY-EFFICIENT LDPC DECODING 审中-公开
标题翻译：存储器高效的LDPC解码
公开(公告)号：WO2008142683A2
公开(公告)日：2008-11-27
申请号：PCT/IL2008/000685
申请日：2008-05-20
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , SHARON, Eran , LITSYN, Simon , ALROD, Idan
发明人： SHARON, Eran , LITSYN, Simon , ALROD, Idan
IPC分类号： H03M13/11
CPC分类号： H03M13/114 , H03M13/6505
摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N-K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.
摘要翻译：为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大存储的软估计数是具有最多位节点的子图中的比特节点的数量。

47. 发明申请

WO2008081426A1 AVOIDING ERRORS IN A FLASH MEMORY BY USING SUBSTITUTION TRANSFORMATIONS 审中-公开
标题翻译：通过替换转换避免FLASH存储器中的错误
公开(公告)号：WO2008081426A1
公开(公告)日：2008-07-10
申请号：PCT/IL2007/001567
申请日：2007-12-19
申请人： RAMOT AT TEL AVIV UNIVERSITY LTD. , ALROD, Idan , SHARON, Eran , LITSYN, Simon
发明人： ALROD, Idan , SHARON, Eran , LITSYN, Simon
IPC分类号： G06F11/10 , G11C7/10 , G11C11/56
CPC分类号： G11C11/5628 , G06F11/1072 , G11C7/1006 , G11C29/00
摘要： Memory circuitry, or a memory device controller, or a host of a memory device, store an input string of M N-tuples of bits by selecting a substitution transformation in accordance with the input string and by applying the transformation to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the circuitry selectively programs each of M or more cells to a respective one of 2N states. The circuitry or the controller selects a mapping that maps the binary numbers in [0,2N-1] into respective states in accordance with the input string and the circuitry uses the mapping to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.
摘要翻译：存储器电路或存储器装置控制器或存储器装置的主机通过根据输入串并通过选择替换变换来存储M个N比特元组的输入串对输入字符串进行转换以提供M个N元组比特的变换串。将M个或更多个存储器单元编程为表示转换后的字符串，并且优选地还表示转换的关键字。或者，电路选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应一个。电路或控制器根据输入串选择将[0,2N-1]中的二进制数映射到相应状态的映射，并且电路使用该映射来编程M个单元以表示输入串。优选地，映射的关键字与M个单元相关联地存储在存储器中。

48. 发明申请

WO2007057885A2 METHOD AND DEVICE FOR MULTI PHASE ERROR-CORRECTION 审中-公开
标题翻译：用于多相位错误校正的方法和装置
公开(公告)号：WO2007057885A2
公开(公告)日：2007-05-24
申请号：PCT/IL2006/001305
申请日：2006-11-13
申请人： RAMOT AT TEL-AVIV UNIVERSITY LTD. , LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menachem
发明人： LITSYN, Simon , SHARON, Eran , ALROD, Idan , LASSER, Menachem
IPC分类号： H04K1/02
CPC分类号： H03M13/2927 , G06F11/1068 , H03M13/1111 , H03M13/152 , H03M13/1545 , H03M13/2903 , H03M13/2906 , H03M13/3715 , H03M13/6362
摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.
摘要翻译：要编码的数据位被分割成多个子组。每个子组被分别编码以产生相应的码字。所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。最终码字是缩短的码字和浓缩比特的组合。最终码字的表示被分割成选定的子集和多个剩余子集。每个剩余子集被单独解码。如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。如果编码和解码是系统的，则所选择的子集是奇偶校验位。

49. 发明申请

WO2005099209A3 DUAL CARRIER MODULATOR FOR A MULTIBAND OFDM TRANSCEIVER 审中-公开
公开(公告)号：WO2005099209A3
公开(公告)日：2005-10-20
申请号：PCT/EP2005/003574
申请日：2005-04-05
申请人： INFINEON TECHNOLOGIES AG , ERLICH, Yossi , LITSYN, Simon , SHARON, Eran
发明人： ERLICH, Yossi , LITSYN, Simon , SHARON, Eran
IPC分类号： H04L27/26
摘要： Dual Carrier Modulator (DCM) for a Multiband OFDM (Orthogonal Frequency Division Multiplexing) Transceiver of a Ultra Wide Band (UWB) wireless personal access network transmitting OFDM modulated symbols, wherein each OFDM symbol is modulated by a predetermined number (N CBPS ) of encoded bits, said Dual Carrier Modulator (1) comprising: (g) a grouping unit (1-1) for grouping N CBPS encoded bits of a serial bit stream into bit groups each having a predetermined number (m) of bits; (h) a mapping unit (1-2) for mapping each bit group received from said grouping unit to complex symbols(y) using an orthogonal transform; and (i) a reordering unit (1-3) for reordering the complex symbols (y) mapped by said mapping unit, wherein each complex symbol (y) is provided to modulate a corresponding data tone of an OFDM symbol.

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