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31. 发明申请

WO2008021530A2 NETWORK DIRECT MEMORY ACCESS 审中-公开
标题翻译：网络直接存储器访问
公开(公告)号：WO2008021530A2
公开(公告)日：2008-02-21
申请号：PCT/US2007018329
申请日：2007-08-17
申请人： PA SEMI INC , DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
发明人： DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one or more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统至少包括耦合到网络的第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器存取（DMA）控制器。第一节点被配置为向第二节点传输至少第一分组以访问本地存储器中的数据以及未被编码以访问本地存储器的至少一个其他分组。所述第二节点被配置为从协议栈的数据链路层捕获所述分组，并且其中所述DMA控制器被配置为响应于所述第一分组与所述本地存储器进行一次或多次传送以访问由所述第一分组指定的数据从数据链路层接收。第二个节点配置为将另一个数据包处理到协议栈的顶部。

32. 发明申请

WO2007062004A3 METHODS, MEDIA, AND DEVICES FOR MOVING A CONNECTION FROM ONE POINT OF ACCESS TO ANOTHER POINT OF ACCESS 审中-公开
标题翻译：用于从一个接入点到另一个接入点移动连接的方法，媒体和设备
公开(公告)号：WO2007062004A3
公开(公告)日：2007-07-12
申请号：PCT/US2006045000
申请日：2006-11-20
申请人： UNIV COLUMBIA , FORTE ANDREA G , SCHULZRINE HENNING G
发明人： FORTE ANDREA G , SCHULZRINE HENNING G
IPC分类号： H04B7/00 , H04W28/18 , H04W36/08 , H04W76/02 , H04W92/20
CPC分类号： H04W36/08 , H04L12/1886 , H04L47/125 , H04L49/109 , H04W36/0011 , H04W36/0016 , H04W36/0055 , H04W36/0061 , H04W84/18 , H04W92/20
摘要： Systems, methods, media, and devices for providing cooperation among digital processing devices in wireless networks are provided. In some embodiments, methods for moving a connection from one point of access to another point of access are provided, sending a request for information from a first mobile node to at least one other node, wherein the request for information contains first information identifying at least one point of access; receiving a response containing second information identifying at least one point of access from the at least one other node; and establishing a connection between the first mobile node and a point of access identified in the second information, hi some embodiments, devices that can move a connection from one point of access to another point of access are provided.
摘要翻译：提供了用于在无线网络中的数字处理设备之间提供协作的系统，方法，媒体和设备。在一些实施例中，提供了用于将连接从一个接入点移动到另一个接入点的方法，从第一移动节点向至少一个其他节点发送信息请求，其中信息请求包含至少标识至少一个访问点; 从所述至少一个其他节点接收包含识别至少一个访问点的第二信息的响应; 以及建立第一移动节点与在第二信息中标识的接入点之间的连接。在一些实施例中，提供可以将连接从一个接入点移动到另一个接入点的设备。

33. 发明申请

WO2007062004A2 METHODS, MEDIA, AND DEVICES FOR MOVING A CONNECTION FROM ONE POINT OF ACCESS TO ANOTHER POINT OF ACCESS 审中-公开
标题翻译：方法，媒体和设备，用于移动从一个访问点到另一个访问点的连接
公开(公告)号：WO2007062004A2
公开(公告)日：2007-05-31
申请号：PCT/US2006/045000
申请日：2006-11-20
申请人： THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK , FORTE, Andrea, G. , SCHULZRINE, Henning, G.
发明人： FORTE, Andrea, G. , SCHULZRINE, Henning, G.
IPC分类号： H04Q7/24
CPC分类号： H04W36/08 , H04L12/1886 , H04L47/125 , H04L49/109 , H04W36/0011 , H04W36/0016 , H04W36/0055 , H04W36/0061 , H04W84/18 , H04W92/20
摘要： Systems, methods, media, and devices for providing cooperation among digital processing devices in wireless networks are provided. In some embodiments, methods for moving a connection from one point of access to another point of access are provided, sending a request for information from a first mobile node to at least one other node, wherein the request for information contains first information identifying at least one point of access; receiving a response containing second information identifying at least one point of access from the at least one other node; and establishing a connection between the first mobile node and a point of access identified in the second information, hi some embodiments, devices that can move a connection from one point of access to another point of access are provided.
摘要翻译：提供了用于在无线网络中的数字处理设备之间提供协作的系统，方法，媒体和设备。在一些实施例中，提供了用于将连接从一个接入点移动到另一个接入点的方法，将对来自第一移动节点的信息的请求发送到至少一个其他节点，其中对信息的请求包含第一信息，一个访问点; 接收包含识别来自所述至少一个其他节点的至少一个接入点的第二信息的响应; 以及在第一移动节点和第二信息中标识的接入点之间建立连接。在一些实施例中，提供了可以将连接从一个接入点移动到另一个接入点的设备。

34. 发明申请

WO2006106476A1 NETWORK-ON-CHIP ENVIRONMENT AND METHOD FOR REDUCTION OF LATENCY 审中-公开
标题翻译：网络在线环境和减少延迟的方法
公开(公告)号：WO2006106476A1
公开(公告)日：2006-10-12
申请号：PCT/IB2006/051013
申请日：2006-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N. V. , GANGWAL, Om Prakash
发明人： GANGWAL, Om Prakash
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/254 , G06F15/7825 , H04L45/40 , H04L49/109 , H04L49/205
摘要： The invention relates to an integrated circuit comprising a plurality of processing modules (21, 23, M, S; IP) and a network (NoC) arranged for coupling processing modules (21, 23, M, S; IP), comprising: the processing module (21, 23, M, S; IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) supplied by the associated processing module and for receiving data from the network (NoC) destined for the associated processing module; wherein the data transmission between processing modules (21, 23, M, S; IP) operates based on time division multiple access (TDMA) using time slots; each network interface (NI) includes a slot table for storing an allocation of a time slot to a connection (C1-C4), wherein multiple connections (C1-C4) are provided between a first processing module (21, M, IP) and a second processing module ( 23, S, IP) and a sharing of time slots allocated to these multiple connections between the first and a second processing modules is provided. The invention use the idea to utilize all or a part of time slots in common, which are allocated for multiple connections between a first and a second processing module, in order to reduce the latency of such connections. By sharing of slots assigned to multiple connections between two processing module a large pool of slots during one revolution of a slot table is formed. Thus the latency to access a burst of data could be reduced.
摘要翻译：本发明涉及一种集成电路，它包括多个处理模块（21,23，M，S; IP）和一个网络（NoC），用于耦合处理模块（21,23，M，S; IP），包括：处理模块（21,23，M，S; IP）包括相关联的网络接口（NI），其被提供用于将数据发送到由相关处理模块提供的网络（NoC），并用于从目标地址（NoC）接收数据用于相关处理模块; 其中处理模块（21,23，M，S; IP）之间的数据传输基于使用时隙的时分多址（TDMA）操作; 每个网络接口（NI）包括用于存储对连接（C1-C4）的时隙分配的时隙表，其中在第一处理模块（21，M，IP）和提供第二处理模块（23，S，IP）以及分配给第一和第二处理模块之间的这些多个连接的时隙的共享。本发明使用该思想来利用共同的全部或部分时隙，这些时隙被分配用于第一和第二处理模块之间的多个连接，以便减少这种连接的等待时间。通过共享分配给两个处理模块之间的多个连接的时隙，形成在一个时隙表的一圈内的大量时隙池。因此，可以减少访问数据突发的延迟。

35. 发明申请

WO0003522A9 A METHOD OF SENDING PACKETS BETWEEN TRUNK PORTS OF NETWORK SWITCHES 审中-公开
标题翻译：在网络交换机的端口端口之间发送分组的方法
公开(公告)号：WO0003522A9
公开(公告)日：2000-05-18
申请号：PCT/US9914824
申请日：1999-06-30
申请人： BROADCOM CORP
发明人： KADAMBI SHIRI , AMBE SHEKHAR
IPC分类号： G06F17/30 , H04L12/18 , H04L12/28 , H04L12/42 , H04L12/46 , H04L12/50 , H04L12/56 , H04L29/06 , H04L29/08 , H04L12/66
CPC分类号： H04L12/5601 , H04L12/18 , H04L12/42 , H04L12/46 , H04L12/4625 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L12/56 , H04L12/5602 , H04L29/06 , H04L45/00 , H04L45/24 , H04L45/245 , H04L45/742 , H04L47/10 , H04L47/125 , H04L47/2408 , H04L47/2441 , H04L47/2458 , H04L47/30 , H04L47/50 , H04L47/522 , H04L47/525 , H04L47/6205 , H04L47/6215 , H04L47/6225 , H04L47/623 , H04L49/102 , H04L49/103 , H04L49/107 , H04L49/108 , H04L49/109 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3036 , H04L49/3072 , H04L49/3081 , H04L49/309 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/602 , H04L49/606 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9057 , H04L49/9073 , H04L67/10 , H04L69/14 , H04L69/16 , H04L69/161 , H04L69/323 , H04L69/329 , H04L2012/5651 , H04L2012/5665 , H04L2012/5667 , H04L2012/5679 , H04L2012/568 , H04L2012/5682 , H04L2012/5683 , Y02D50/30 , Y10S707/99931 , Y10S707/99945
摘要： The present invention is directed to a system and method of sending packets between ports on trunked network switches. The method includes providing a first switch having a plurality of communication ports thereupon, and providing a second switch having a plurality of communication ports thereupon. A trunk connection is provided between the first switch and the second switch, with the trunk connection including at least two of the plurality of ports from the first switch being connected to at least two of the plurality of ports of the second switch. A rules table (32) is provided, defining a set of rules identifying which port of the trunk connection will be used for communication. A packet is sent from a first port on the first switch to a second port on the second switch. The packet is received at an ingress submodule of the first switch, and a lookup is performed on one of a source address and a destination address of the packet based upon a lookup table provided in the ingress submodule.
摘要翻译：本发明涉及在集群网络交换机上的端口之间发送分组的系统和方法。该方法包括提供具有多个通信端口的第一交换机，以及提供具有多个通信端口的第二交换机。在第一交换机和第二交换机之间提供中继线连接，其中中继线连接包括来自第一交换机的多个端口中的至少两个连接到第二交换机的多个端口中的至少两个端口。规则表（32）被提供，定义一组规则来识别中继线连接的哪个端口将被用于通信。数据包从第一个交换机上的第一个端口发送到第二个交换机上的第二个端口。该分组在第一交换机的入口子模块处被接收，并且基于在入口子模块中提供的查找表对分组的源地址和目的地址中的一个执行查找。

36. 发明申请

WO2018111420A1 SYSTEMS AND METHODS FOR IMMEDIATE TRANSMISSION AFTER CLEAR CHANNEL ASSESSMENT 审中-公开
公开(公告)号：WO2018111420A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/058799
申请日：2017-10-27
申请人： QUALCOMM INCORPORATED
发明人： DENBOER, Paul , DENBOER, Huibert , CHARI, Sriraman , MCFARLAND, William
IPC分类号： H04W74/08 , H04W88/06
CPC分类号： H04W74/085 , H04L7/033 , H04L49/109 , H04W4/80 , H04W72/10 , H04W74/0808 , H04W88/06
摘要： A method is described. The method includes receiving a clear channel assessment (CCA) using a first radio configured for a first communication protocol. The method also includes reconfiguring a second radio configured for a second communication protocol for transmission of the first communication protocol. The method further includes transmitting immediately using the second radio after receiving the CCA, wherein a CCA measurement indicates that a channel is clear.

37. 发明申请

WO2017120270A1 MASSIVELY PARALLEL COMPUTER, ACCELERATED COMPUTING CLUSTERS, AND TWO DIMENSIONAL ROUTER AND INTERCONNECTION NETWORK FOR FIELD PROGRAMMABLE GATE ARRAYS, AND APPLICATIONS 审中-公开
标题翻译：大型并行计算机，加速计算集群，以及用于现场可编程门阵列的二维路由器和互连网络，以及应用
公开(公告)号：WO2017120270A1
公开(公告)日：2017-07-13
申请号：PCT/US2017/012230
申请日：2017-01-04
申请人： GRAY RESEARCH LLC
发明人： GRAY, Jan Stephen
IPC分类号： H04L12/933 , H04L12/931
CPC分类号： G06F13/36 , G06F13/4068 , H04L49/109
摘要： An embodiment of a massively parallel computing system comprising a plurality of processors, which may be subarranged into clusters of processors, and interconnected by means of a configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The system further comprises diverse high bandwidth external I/O devices and interfaces, which may include without limitation Ethernet interfaces, and dynamic RAM (DRAM) memories. The system is designed for implementation in programmable logic in FPGAs, but may also be implemented in other integrated circuit technologies, such as non programmable circuitry, and in integrated circuits such as application specific integrated circuits (ASICs). The system enables the practical implementation of diverse FPGA computing accelerators to speed up computation for example in data centers or telecom networking infrastructure. The system uses the NOC to interconnect processors, clusters, accelerators, and/or external interfaces. A great diversity of NOC client cores, for communication amongst various external interfaces and devices, and on-chip interfaces and resources, may be coupled to a router in order to efficiently communicate with other NOC client cores. The system, router, and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.
摘要翻译：公开了包括多个处理器的大规模并行计算系统的实施例，其可以被子排列成处理器群并且通过用于芯片上网络（NOC）的可配置定向2D路由器互连。该系统还包括不同的高带宽外部I / O设备和接口，其可以包括但不限于以太网接口和动态RAM（DRAM）存储器。该系统设计用于在FPGA中的可编程逻辑中实现，但也可以在其他集成电路技术（例如非可编程电路）以及诸如专用集成电路（ASIC）的集成电路中实现。该系统能够实现多种FPGA计算加速器的实际实施，以加速计算，例如在数据中心或电信网络基础设施中。系统使用NOC互连处理器，集群，加速器和/或外部接口。为了与其他NOC客户端核心进行有效通信，可以将各种NOC客户端核心（用于各种外部接口和设备之间的通信以及片上接口和资源）耦合到路由器。系统，路由器和NOC可以在芯片上实现大型集成系统的可行FPGA实现，通过高带宽链路（包括计算和加速器内核，工业标准IP内核，DRAM / HBM / HMC通道，PCI Express通道等）互连数百个客户端内核。和10G / 25G / 40G / 100G / 400G网络。

38. 发明申请

WO2017053091A1 CONFIGURABLE AND SCALABLE BUS INTERCONNECT FOR MULTI-CORE, MULTI-THREADED WIRELESS BASEBAND MODEM ARCHITECTURE 审中-公开
标题翻译：多核，多线无线基带调制解调器架构的可配置和可扩展总线互连
公开(公告)号：WO2017053091A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/051085
申请日：2016-09-09
申请人： QUALCOMM INCORPORATED
发明人： CHENG, Scott Wang-Yip , KHAN, Raheel , BANTVAL, Vijay , BAHN, Jun Ho
IPC分类号： H04L12/933 , H04L12/42
CPC分类号： H04L45/74 , H04L1/0018 , H04L12/4135 , H04L12/42 , H04L12/4637 , H04L45/22 , H04L45/306 , H04L49/102 , H04L49/109
摘要： Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.
摘要翻译：本公开的各个方面描述了一种配置在环路中以将数据路由到实现调制解调器功能的处理器的双向双互连总线。多个节点可以被耦合以形成包括至少两个互连环的环形总线。可以将多个处理器分配给多个节点。多个处理器中的第一处理器可以被配置为处理第一数据类型，并且多个处理器中的第二处理器可以被配置为处理第二数据类型。环形总线上的数据可以被分成第一数据类型和第二数据类型，并且第一数据类型的分离数据可以在一个互连环上被路由到第一处理器，并且第二数据类型的分离数据可以被路由到另一个互连环到第二处理器。

39. 发明申请

WO2016105967A1 MITIGATING TRAFFIC STEERING INEFFICIENCIES IN DISTRIBUTED UNCORE FABRIC 审中-公开
标题翻译：在分销的UNCORE FABRIC中减少交通转向失效
公开(公告)号：WO2016105967A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/065138
申请日：2015-12-11
申请人： INTEL CORPORATION
发明人： NAGARAJAN, Ramadass , FREDERICK, Michael Todd
IPC分类号： G06F13/16 , G06F12/08
CPC分类号： H04L49/25 , G06F15/7807 , H04L45/7453 , H04L49/109 , H04L49/356
摘要： In an example, selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system is divided into two independent pipelines. Each pipeline operates independently of the other pipeline, and each accesses only one-half of the system memory, such as even or odd addresses in an interleaved memory. The two pipelines do not reconverge until after memory values have been returned. However, the uncore fabric may still present a single, monolithic interface to requesting devices. This allows system designers to treat the uncore fabric as a "black box" without modifying existing designs. Each incoming address may be processed by a deterministic hash, assigned to one of the pipelines, processed through memory, and then passed to a credit return.
摘要翻译：在一个示例中，片上系统（SoC）或其他嵌入式系统的非空心结构的选定部分被分成两个独立的管道。每个流水线独立于其他流水线运行，并且每个流水线仅访问系统存储器的一半，例如交错存储器中的偶数或奇数地址。在返回内存值之后，两条管道不会重新映射。然而，不织布可能仍然呈现出一个单一的接口来请求设备。这使得系统设计人员可以将不干净的织物视为“黑匣子”，而无需修改现有设计。每个传入地址可以通过确定性散列来处理，分配给一条管道，通过存储器处理，然后传递给信用回报。

40. 发明申请

WO2016099795A1 SPATIALLY DIVIDED CIRCUIT-SWITCHED CHANNELS FOR A NETWORK-ON-CHIP 审中-公开
标题翻译：用于网路芯片的空间分路电路切换通道
公开(公告)号：WO2016099795A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/061712
申请日：2015-11-20
申请人： INTEL CORPORATION
发明人： KAUL, Himanshu , CHEN, Gregory, K. , ANDERS, Mark, A.
IPC分类号： H04L12/771 , H04L12/931 , G06F13/14
CPC分类号： H04L47/724 , G06F15/7825 , H04L12/50 , H04L12/6402 , H04L12/66 , H04L49/109 , H04L49/3018 , H04L49/3027
摘要： An apparatus may comprise a plurality of ports and a plurality of channel reservation banks. A channel reservation bank is to be associated with a port of the plurality of ports. The channel reservation bank is to comprise a plurality of channel reservation slots. The port of the plurality of ports is to comprise a plurality of circuit-switched channels through the port. The configuration of each of the plurality of circuit-switched channels to be based on information stored in a channel reservation slot of the channel reservation bank to be associated with the port.
摘要翻译：装置可以包括多个端口和多个信道预留库。信道预留库将与多个端口的端口相关联。信道预约库包括多个信道预留时隙。多个端口的端口包括通过端口的多个电路交换信道。多个电路交换信道中的每一个的配置将基于存储在与端口相关联的信道预留库的信道预留时隙中的信息。

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