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1. 发明申请

WO2008021530A2 NETWORK DIRECT MEMORY ACCESS 审中-公开
标题翻译：网络直接存储器访问
公开(公告)号：WO2008021530A2
公开(公告)日：2008-02-21
申请号：PCT/US2007018329
申请日：2007-08-17
申请人： PA SEMI INC , DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
发明人： DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one or more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统至少包括耦合到网络的第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器存取（DMA）控制器。第一节点被配置为向第二节点传输至少第一分组以访问本地存储器中的数据以及未被编码以访问本地存储器的至少一个其他分组。所述第二节点被配置为从协议栈的数据链路层捕获所述分组，并且其中所述DMA控制器被配置为响应于所述第一分组与所述本地存储器进行一次或多次传送以访问由所述第一分组指定的数据从数据链路层接收。第二个节点配置为将另一个数据包处理到协议栈的顶部。

2. 发明申请

WO2007022019A3 PARTIALLY POPULATED, HIERARCHICAL CROSSBAR 审中-公开
标题翻译：部分人口，分级交叉
公开(公告)号：WO2007022019A3
公开(公告)日：2007-05-31
申请号：PCT/US2006031521
申请日：2006-08-11
申请人： PA SEMI INC , SUBRAMANIAN SRIDHAR P , KELLER JAMES B , YIU GEORGE KONG , WADHAWAN RUCHI
发明人： SUBRAMANIAN SRIDHAR P , KELLER JAMES B , YIU GEORGE KONG , WADHAWAN RUCHI
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/364 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments. The arbiter is configured to arbitrate among a subset of requests for which each segment in the corresponding communication path is available.
摘要翻译：在各种实施例中，一种设备包括多个代理和互连。在一个实施例中，多个代理包括第一至第四代理。互连包括可切换（例如，使用多个选择电路）以形成代理之间的通信路径的多个段，并且第一段被包括在从第一代理到第二代理的第一通信路径中，并且也是包括在从第三代理到第四代理的第二通信路径中。在另一个实施例中，每个段由选择电路驱动。至少一个选择电路具有至少一个区段和来自至少一个代理的输出作为输入。在又一个实施例中，仲裁器被配置为通过这些段确定用于到目的地代理的每个请求代理的互连上的通信路径。仲裁器被配置为在相应通信路径中的每个段可用的请求的子集中进行仲裁。

3. 发明申请

WO2009042257A3 BUFFER MINIMIZATION IN INTERFACE CONTROLLER 审中-公开
标题翻译：接口控制器中的缓冲器最小化
公开(公告)号：WO2009042257A3
公开(公告)日：2009-07-16
申请号：PCT/US2008065553
申请日：2008-06-02
申请人： PA SEMI INC , WANG JAMES
发明人： WANG JAMES
IPC分类号： H04L12/66 , G06F13/40
CPC分类号： H04L12/66
摘要： In one embodiment, an apparatus comprises serializer/deserializer (SERDES) circuits. Each SERDES circuit is configured to transmit data on a respective lane to which the SERDES circuit is are coupled during use. The apparatus further comprises a transmit pipe coupled to the SERDES circuits. The transmit pipe comprises stages, and each stage is configured to process a maximum bandwidth unit (a maximum width of a port that is configurable on the lanes and smaller than a largest packet transmitted on the ports). In another embodiment, the apparatus comprises a transmit command queue; a transmit scheduler coupled to the transmit command queue; and a storage device coupled to the transmit scheduler that stores a scheduling calendar. The transmit scheduler is configured to schedule maximum bandwidth units for transmission on ports configured over the lanes on which packets are transmitted. The maximum bandwidth unit is smaller than a packet and is a maximum width of a port that is configurable on the lanes. The transmit scheduler is configured to schedule the maximum bandwidth units according to the scheduling calendar.
摘要翻译：在一个实施例中，一种装置包括串行器/解串器（SERDES）电路。每个SERDES电路被配置为在使用期间在SERDES电路耦合到的相应通道上传输数据。该设备还包括耦合到SERDES电路的发送管道。发送管道包括多个级，并且每个级被配置为处理最大带宽单位（在通道上可配置的端口的最大宽度并小于在端口上传输的最大数据包）。在另一个实施例中，该装置包括发送命令队列; 传输调度器，其耦合到所述传输命令队列; 以及耦合到传输调度器的存储设备，其存储调度日历。发送调度器被配置为调度最大带宽单位以在通过其上发送分组的通道上配置的端口上传输。最大带宽单位小于数据包，并且是可在通道上配置的端口的最大宽度。发送调度器被配置为根据调度日历来调度最大带宽单位。

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