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1. 发明申请

WO2008021530A3 NETWORK DIRECT MEMORY ACCESS 审中-公开
公开(公告)号：WO2008021530A3
公开(公告)日：2008-02-21
申请号：PCT/US2007/018329
申请日：2007-08-17
申请人： P.A. SEMI, INC. , DESAI, Shailendra, S. , HAYTER, Mark, D. , GO, Dominic
发明人： DESAI, Shailendra, S. , HAYTER, Mark, D. , GO, Dominic
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

2. 发明申请

WO2012078334A1 INTERRUPT DISTRIBUTION SCHEME 审中-公开
标题翻译：中断分配方案
公开(公告)号：WO2012078334A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/061197
申请日：2011-11-17
申请人： APPLE INC. , DE CESARE, Josh P. , WADHAWAN, Ruchi , MACHNICKI, Erik P. , HAYTER, Mark D.
发明人： DE CESARE, Josh P. , WADHAWAN, Ruchi , MACHNICKI, Erik P. , HAYTER, Mark D.
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2424 , Y02D10/14
摘要： In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.
摘要翻译：在一个实施例中，中断控制器可以实现用于在多个处理器之间分配中断的中断分配方案。该方案可以考虑在确定哪个处理器应该接收给定中断时的各种处理器状态。例如，处理器状态可以包括处理器是否处于休眠状态，中断是否被使能，处理器是否响应先前的中断等。中断控制器可以实现超时机制以检测到中断被延迟（例如，在提供给处理器之后）。中断可能会在超时到期时重新评估，并可能提供给另一个处理器。中断控制器可以被配置为自动并原子地屏蔽中断，以响应于将中断的中断向量传递给响应处理器。

3. 发明申请

WO2007041301A1 UNIFIED DMA 审中-公开
标题翻译：统一DMA
公开(公告)号：WO2007041301A1
公开(公告)日：2007-04-12
申请号：PCT/US2006/038081
申请日：2006-09-29
申请人： P.A. SEMI, INC. , GO, Dominic , HAYTER, Mark, D. , CHEN, Zongijan , WADHAWAN, Ruchi , KU, Weichun
发明人： GO, Dominic , HAYTER, Mark, D. , CHEN, Zongijan , WADHAWAN, Ruchi , KU, Weichun
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.
摘要翻译：在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器以及耦合到DMA控制器的主机。第一接口电路被配置为根据协议在接口上进行通信。主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输。

4. 发明申请

WO2007025192A1 EXPLICIT FLOW CONTROL IN A GIGABIT/10 GIGABIT ETHERNET SYSTEM 审中-公开
标题翻译：一个GIGABIT / 10 GIGABIT以太网系统中的显示流量控制
公开(公告)号：WO2007025192A1
公开(公告)日：2007-03-01
申请号：PCT/US2006/033329
申请日：2006-08-24
申请人： P.A. SEMI, INC. , DESAI, Shailendra, S. , HAYTER, Mark, D.
发明人： DESAI, Shailendra, S. , HAYTER, Mark, D.
IPC分类号： H04L12/56
CPC分类号： H04L47/245 , H04L47/10 , H04L47/13
摘要： In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.
摘要翻译：在一个实施例中，系统包括通信介质; 耦合到所述通信介质的第一控制器; 以及耦合到所述通信介质的第二控制器。第一控制器被配置为在传送分组的第一部分之后中断在通信介质上的分组到第二控制器的传输。第一控制器被配置为响应于中断分组的传输而在通信介质上发送至少一个控制符号，并且其中第一控制器被配置为继续使用分组的第二部分传输分组。在一些实施例中，控制器可以包括媒体访问控制器和物理编码子层。

5. 发明申请

WO2008021530A2 NETWORK DIRECT MEMORY ACCESS 审中-公开
标题翻译：网络直接存储器访问
公开(公告)号：WO2008021530A2
公开(公告)日：2008-02-21
申请号：PCT/US2007018329
申请日：2007-08-17
申请人： PA SEMI INC , DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
发明人： DESAI SHAILENDRA S , HAYTER MARK D , GO DOMINIC
IPC分类号： H04L12/56 , G06F13/28 , H04L29/08
CPC分类号： H04L49/35 , H04L49/109 , H04L49/352 , H04L69/324
摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one or more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.
摘要翻译：在一个实施例中，系统至少包括耦合到网络的第一节点和第二节点。第二节点包括本地存储器和耦合到本地存储器的直接存储器存取（DMA）控制器。第一节点被配置为向第二节点传输至少第一分组以访问本地存储器中的数据以及未被编码以访问本地存储器的至少一个其他分组。所述第二节点被配置为从协议栈的数据链路层捕获所述分组，并且其中所述DMA控制器被配置为响应于所述第一分组与所述本地存储器进行一次或多次传送以访问由所述第一分组指定的数据从数据链路层接收。第二个节点配置为将另一个数据包处理到协议栈的顶部。

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