专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明申请

WO2004109807A3 SEMICONDUCTOR STRUCTURE COMPRISING INTEGRATED DOPING CHANNELS 审中-公开
标题翻译：具有集成的融资渠道半导体结构
公开(公告)号：WO2004109807A3
公开(公告)日：2005-02-10
申请号：PCT/DE2004001070
申请日：2004-05-18
申请人： HAHN MEITNER INST BERLIN GMBH , FINK DIETMAR , HOPPE KURT , PETROV ALEXANDER , FAHRNER WOLFGANG , ULYASHIN ALEXANDER , STANSKI BERNHARD , SANDKUEHLER ULRICH
发明人： FINK DIETMAR , HOPPE KURT , PETROV ALEXANDER , FAHRNER WOLFGANG , ULYASHIN ALEXANDER , STANSKI BERNHARD , SANDKUEHLER ULRICH
IPC分类号： G01N27/00 , G01N27/12 , G01N27/414 , H01L21/316 , H01L29/772 , H01L29/86 , H01L31/10 , H01L51/00 , H01L51/30 , H01L51/20
CPC分类号： H01L51/0508 , B82Y10/00 , G01N27/129 , H01L21/31695 , H01L29/772 , H01L29/86 , H01L51/0046 , H01L51/0078 , H01L51/428 , Y02E10/549 , Y02P70/521
摘要： To obtain the greatest degree of flexibility and maximise its universal applicability, the inventive parameterised semiconductor composite structure (TEMPOS) has nanoscalar pores (VP) acting as doping channels and a high-ohmic coating of electrically conductive material (ECM), which also extends between the pores (VP), on the surface of the layer (EIL) that consists of an electrically insulating material. An electric resistance is generated, said resistance supporting the vertical migration of additional charge carriers into the semiconductor composite structure (PSC) but preventing horizontal migration between the equilateral electrodes (o, w). Fundamental parameters for regulating the function of the semiconductor composite structure (TEMPOS), which can also comprise a differentially negative resistance behaviour (NERPOS), relate to the configuration of the pores (VP) and the electrically conductive material (ECM). Preferably, the pores (VP) can be created by ion irradiation and subsequent etching, the etching duration determining the pore depth and pore diameter.
摘要翻译：为了实现与最大普遍性最大的灵活性，根据本发明（TEMPO）作为掺杂剂通道纳米尺度的孔（VP）和导电材料（ECM）的高电阻涂层还该层的表面上的孔（VP）之间的参数化半导体复合结构（EIL ）电绝缘材料，其特征在于，产生一个电阻，它支持的额外电荷载流子垂直迁移（在半导体复合结构PSC），水平（在电极之间的等边O，W）但阻止。用于半导体复合结构的功能设置（TEMPO）基本参数，其也可以包括差分负电阻特性（NERPOS），指的是孔（VP）和导电材料（ECM）的配置。优选地，所述孔（VP）可以通过离子辐照，接着通过蚀刻，其中所述刻蚀时间决定细孔的深度，和孔径来制造。

32. 发明申请

WO2004019414A1 TRI-GATE DEVICES AND METHODS OF FABRICATION 审中-公开
标题翻译：三门装置和制造方法
公开(公告)号：WO2004019414A1
公开(公告)日：2004-03-04
申请号：PCT/US2003/026242
申请日：2003-08-22
申请人： INTEL CORPORATION
发明人： CHAU, Robert , DOYLE, Brian , KAVALIEROS, Jack , BARLAGE, Douglas , DATTA, Suman
IPC分类号： H01L29/423
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1033 , H01L29/41791 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66795 , H01L29/772 , H01L29/7854 , H01L29/78645 , H01L29/78696 , H01L51/0048 , H01L51/0554 , Y10S977/742 , Y10S977/842 , Y10S977/938
摘要： The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
摘要翻译：本发明是一种半导体器件，其包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。栅电介质层形成在半导体本体的顶表面和半导体本体的横向相对的侧壁上。栅极电极形成在半导体本体的顶表面上的栅电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。

33. 发明申请

WO1997012402A1 SEMICONDUCTOR CHARGE POTENTIAL WELLS WITH INTEGRATED DIFFUSIONS 审中-公开
标题翻译：具有集成扩散的半导体充电电位阱
公开(公告)号：WO1997012402A1
公开(公告)日：1997-04-03
申请号：PCT/US1996015285
申请日：1996-09-24
申请人： ANALOG DEVICES, INC.
发明人： ANALOG DEVICES, INC. , MUNROE, Scott, C.
IPC分类号： H01L29/768
CPC分类号： H01L29/76816 , H01L29/42396 , H01L29/768 , H01L29/772 , H01L29/7831 , H01L29/94
摘要： A semiconductor device having a semiconductor region including a material of a first predetermined conductivity type; an insulating layer (40) provided on the semiconductor region; a gate electrode (32, 34, 38) provided on the insulating layer, the gate electrode forming a potential well within the semiconductor region in response to a potential being applied thereto; and a diffusion (36) of highly doped material of a second predetermined conductivity type being positioned within the semiconductor region, and which is applied through an opening in the gate electrode and the insulating layer (40), the diffusion (36) being in direct ohmic contact with the potential well. The diffusion (36) can be either a n+ or p+ diffusion. The diffusion (36) accommodates a reduction in lateral time constants of charge redistribution within the potential well, direct sensing of the charge in the well, and injection and extraction of charge to and from the well.
摘要翻译：一种半导体器件，具有包括第一预定导电类型的材料的半导体区域; 设置在所述半导体区域上的绝缘层（40）设置在所述绝缘层上的栅极电极，所述栅极电极响应于施加到所述栅电极的电位而在所述半导体区域内形成势阱; 并且第二预定导电类型的高掺杂材料的扩散（36）位于半导体区域内，并且通过栅电极和绝缘层（40）中的开口施加，扩散（36）直接欧姆接触势阱。扩散（36）可以是n +或p +扩散。扩散（36）可以减少潜在井内的电荷再分配的横向时间常数，直接感测井中的电荷，以及向井和从井的注入和提取电荷。

34. 发明申请

WO2019090762A1 半导体结构及其形成方法审中-公开
公开(公告)号：WO2019090762A1
公开(公告)日：2019-05-16
申请号：PCT/CN2017/110695
申请日：2017-11-13
申请人：吴展兴
发明人：吴展兴
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28 , H01L29/772
摘要：一种闸极（1100, 1300）的形成方法，包含形成第一图案化光阻层（310）于基板（200）上；形成间隙壁（510d, 510s）于该第一图案化光阻层（310）的侧壁上，其中该间隙壁（510d, 510s）包含弯曲部分；去除第一图案化光阻层（310）；形成替代光阻层（730）于该基板（200）上，使该间隙壁（510d, 510s）插在该替代光阻层（730）中而露出该弯曲部分；以及去除该间隙壁（510d, 510s）以形成开口（811d, 811s）于该替代光阻层（730）中，其中该开口（811d, 811s）定义闸极（1100, 1300）的底部尺寸。还包含根据上述方法形成的所述的闸极（1100, 1300）结构。

35. 发明申请

WO2018094619A1 一种隧穿晶体管及其制备方法审中-公开
公开(公告)号：WO2018094619A1
公开(公告)日：2018-05-31
申请号：PCT/CN2016/106986
申请日：2016-11-23
申请人：华为技术有限公司
发明人：李伟 , 徐慧龙 , 张臣雄
IPC分类号： H01L29/772 , H01L21/335 , H01L29/08
CPC分类号： H01L29/08 , H01L29/772
摘要：一种隧穿晶体管及其制备方法，该晶体管包括：源极、漏极及异质结；其中，异质结包括层叠的第一导电材料层和第二导电材料层，两个导电材料层中一个为二维材料，另一个为二维或三维材料制作的材料层；源极与第一导电材料层导电连接并与第二导电材料层绝缘，漏极与第二导电材料层电连接且与第一导电材料层绝缘。在上述技术方案中，沟道材料为二维材料，异质结界面势垒较小(小于0.3eV)，增加了隧穿几率，提高隧穿电流。采用局域栅结构，栅极只控制异质结隧穿区域。异质结的形成简单，且该异质结无晶格失配所导致的界面缺陷，能有效抑制泄漏电流。

36. 发明申请

WO2018060015A1 STAR-SHAPED STYRENE POLYMERS WITH ENHANCED GLASS TRANSITION TEMPERATURE 审中-公开
标题翻译：具有增强的玻璃化转变温度的星形苯乙烯聚合物
公开(公告)号：WO2018060015A1
公开(公告)日：2018-04-05
申请号：PCT/EP2017/073688
申请日：2017-09-20
申请人： BASF SE
发明人： MARTIN, Emmanuel , BRUNETTI, Fulvio G. , KAELBLEIN, Daniel , KNOLL, Konrad , KOPPING, Jordan Thomas
IPC分类号： C08F212/08 , C08F212/32 , C09D125/08 , C08F297/04 , H01L29/772
CPC分类号： C08F212/32 , C08F212/08 , C08F297/042 , C09D125/08 , H01L29/772 , H01L51/0035 , H01L51/0095 , H01L51/052 , C08F212/36 , C08F236/06 , C08F2/42
摘要： The present invention provides polymers comprising units of formulae (I) and (II) wherein a wavy line represents a valency, Ar 1 , Ar 2 and Ar 3 are independently from each other C 6-14 -aryl, which can be substituted with 1 to 9 substituents R a , wherein R a is at each occurrence selected from the group consisting of C 1-30 -alkyl, O-C 1-30 -alkyl, C 6-14 -aryl and O-C 6-14 -aryl, and R 1 is H or C 1-4 -alkyl, and at least one an n-valent unit X, wherein n is an integer from 3 to 10, as well as electronic devices comprising these polymers.
摘要翻译：本发明提供了包含式（I）和（II）的单元的聚合物，其中波浪线表示化合价Ar 1，Ar 2， Ar 3和Ar 3彼此独立地是可以被1至9个取代基R a取代的C 6-14芳基，其中 R a在每次出现时选自C 1-30 - 烷基，OC 1-30 - 烷基，C _{6-14芳基和OC 6-14芳基，并且R 1为H或C 1-4 - 烷基和至少一个n价单元X，其中n是3至10的整数，以及包含这些聚合物的电子器件。}

37. 发明申请

WO2017142482A1 HIGH VOLTAGE LOGIC CIRCUIT 审中-公开
标题翻译：高压逻辑电路
公开(公告)号：WO2017142482A1
公开(公告)日：2017-08-24
申请号：PCT/SG2017/050070
申请日：2017-02-16
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , NANYANG TECHNOLOGICAL UNIVERSITY
发明人： CHOI, Pilsoon , BOON, Chirn-Chye , PEH, Li-Shiuan
IPC分类号： H03K19/20 , H01L21/18 , H01L21/335 , H01L21/8258 , H01L27/06 , H01L27/085 , H01L27/092 , H01L29/16 , H01L29/20 , H01L29/68 , H01L29/772 , H03K19/0175 , H03K19/094
CPC分类号： H01L21/18 , H01L21/8258 , H01L27/0688 , H01L27/085 , H01L27/092 , H01L29/16 , H01L29/20 , H01L29/68 , H01L29/772 , H03K19/0175 , H03K19/094 , H03K19/20
摘要： A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.
摘要翻译：用于高电压系统应用的高压逻辑电路包括由第一半导体材料形成的第一器件层并且包括低电压逻辑电路; 以及第二器件层，其由第二不同半导体材料形成并且包括用于从低压逻辑电路的低压逻辑输入生成高压逻辑输出的附加电路的一个或多个组件; 其中第一和第二器件层一体形成。而且，一种逻辑电路包括：低电压逻辑输入; 高电源电压输入; 电路接地电压输入; 高电压输出; 由第一半导体材料制成的第一尾部装置; 以及由第二不同半导体材料制成的第二尾部装置; 其中所述第一和第二尾端装置串联耦合在所述高电压输出和所述电路接地电压输入之间; 并且其中第一尾部装置和第二尾部装置的相应的栅极并联耦合到低电压逻辑输入

38. 发明申请

WO2017004703A1 METHOD OF PRINTING ULTRANARROW-GAP LINES 审中-公开
标题翻译：印刷超声波线的方法
公开(公告)号：WO2017004703A1
公开(公告)日：2017-01-12
申请号：PCT/CA2016/050768
申请日：2016-06-30
申请人： NATIONAL RESEARCH COUNCIL OF CANADA
发明人： CHU, Ta-ya , PY, Christophe , TAO, Ye , ZHANG, Zhiyi , DADVAND, Afshin
IPC分类号： H05K3/12 , B82Y30/00 , C09D11/52 , H01L29/772 , H05K1/16
CPC分类号： C09D11/52 , H01L29/772 , H01L51/0022 , H01L51/0023 , H01L51/0508 , H01L51/105 , H05K1/16
摘要： Disclosed is a method of printing ultranarrow-gap lines of a functional material, such as an electrically conductive silver ink. The method entails providing a substrate having an interlayer coated on the substrate and printing the ultranarrow-gap lines by depositing ink on the interlayer of the substrate, the ink comprising the functional material and a solvent that swells the interlayer to cause the interlayer to bulge at edges of the ink to thereby define embankments that confine the ink.
摘要翻译：公开了一种印刷诸如导电银墨的功能材料的超窄间隙线的方法。该方法需要提供具有涂覆在基材上的中间层的基材，并通过在基材的中间层上沉积油墨来印刷超窄间隙线，该油墨包括功能材料和溶解中间层以使夹层膨胀的溶剂油墨的边缘，从而限定限制油墨的路堤。

39. 发明申请

WO2015068162A1 NANOTUBE BASED TRANSISTOR STRUCTURE, METHOD OF FABRICATION AND USES THEREOF 审中-公开
标题翻译：基于纳米管的晶体管结构，其制造方法及其用途
公开(公告)号：WO2015068162A1
公开(公告)日：2015-05-14
申请号：PCT/IL2014/050966
申请日：2014-11-06
申请人： YEDA RESEARCH AND DEVELOPMENT CO. LTD.
发明人： SHAHAL, Ilani , PECKER, Sharon , BENYAMINI, Avishai , WAISMANN, Jonah , HAMO, Assaf , HONIG, Maayan
IPC分类号： H01L51/00 , C01B31/02 , H01L51/05
CPC分类号： H01L51/0558 , C01B32/16 , H01L22/14 , H01L29/0673 , H01L29/1029 , H01L29/66045 , H01L29/772 , H01L51/0012 , H01L51/0024 , H01L51/003 , H01L51/0031 , H01L51/0045 , H01L51/0048 , H01L51/0508 , H01L51/105
摘要： A method for use in construction of an electronic device and a transistor structure are presented. The method comprising: providing one or more nanotubes grown on a surface of a first substrate; providing a desired electrode arrangement fabricated on a surface of a second substrate. The electrode arrangement comprises at least two elevated source and drain electrodes and one or more gate electrodes located in between said elevated source and drain electrodes. The method also comprises bringing the electrode arrangement on the second substrate to close proximity with the first substrate such that surfaces of the first and second substrates face each other; scanning said first substrate with said electrode arrangement and determining contact of electrodes of the electrode arrangement with a nanotube located on the first substrate; and detaching said nanotube from the first substrate to provide a transistor structure comprising an isolated nanotube between the source and drain electrodes.
摘要翻译：提出了一种用于构造电子器件和晶体管结构的方法。该方法包括：提供在第一基底的表面上生长的一个或多个纳米管; 提供制造在第二基板的表面上的期望的电极布置。电极布置包括至少两个升高的源极和漏极以及位于所述升高的源极和漏极之间的一个或多个栅电极。所述方法还包括使所述第二基板上的所述电极布置与所述第一基板靠近，使得所述第一和第二基板的表面彼此面对; 用所述电极装置扫描所述第一衬底，并且确定所述电极装置的电极与位于所述第一衬底上的纳米管的接触; 以及从所述第一衬底分离所述纳米管，以提供在所述源极和漏极之间包括隔离纳米管的晶体管结构。

40. 发明申请

WO2012025190A1 ELECTROCHEMICALLY-GATED TRANSISTOR AND A METHOD FOR ITS MANUFACTURE 审中-公开
标题翻译：电化学晶体管及其制造方法
公开(公告)号：WO2012025190A1
公开(公告)日：2012-03-01
申请号：PCT/EP2011/003878
申请日：2011-08-03
申请人： KARLSRUHER INSTITUT FÜR TECHNOLOGIE , HAHN, Horst , DASGUPTA, Subho , KRUK, Robert
发明人： HAHN, Horst , DASGUPTA, Subho , KRUK, Robert
IPC分类号： H01L29/78 , H01L29/24 , G01N27/414
CPC分类号： H01L29/24 , B82Y10/00 , H01L27/1292 , H01L29/43 , H01L29/4908 , H01L29/66969 , H01L29/772 , H01L29/7869
摘要： The present invention relates to an electrochemically-gated transistor on a substrate, comprising a source electrode (1), a drain electrode (2), a gate electrode (3), and a transistor channel (4) which is located between the source electrode (1) and the drain electrode (2). A predominantly ionic conductor is provided as an electrolyte (5) which covers the transistor channel (4), which comprises nanoparticles of an inorganic semiconductor. Either the electrolyte (5) covers the gate electrode (3) only to a partial extent or the gate electrode (3), which covers the electrolyte (5), completely covers the transistor channel (4). The present invention further relates to a method for manufacturing such an electrochemically-gated transistor. Such a device is a printable, inorganic nanoparticle-channel field-effect transistor which works like an n-channel enhancement- mode MOSFET (NMOS) as a normally-off device.
摘要翻译：本发明涉及一种基板上的电化学门控晶体管，包括源电极（1），漏电极（2），栅电极（3）和晶体管沟道（4）（1）和漏电极（2）。提供主要为离子导体作为覆盖晶体管沟道（4）的电解质（5），其包括无机半导体的纳米颗粒。电解质（5）仅部分地覆盖栅电极（3），或覆盖电解质（5）的栅电极（3）完全覆盖晶体管沟道（4）。本发明还涉及制造这种电化学门控晶体管的方法。这种器件是可印刷的无机纳米颗粒通道场效应晶体管，其工作方式类似于n沟道增强型MOSFET（NMOS）作为常关器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式