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31. 发明申请

WO01001161A1 FERROELECTRIC FILM PROPERTY MEASURING DEVICE, MEASURING METHOD THEREFOR AND MEASURING METHOD FOR SEMICONDUCTOR MEMORY UNITS 审中-公开
标题翻译：电磁膜性能测量装置，其半导体存储单元的测量方法及其测量方法
公开(公告)号：WO01001161A1
公开(公告)日：2001-01-04
申请号：PCT/JP2000/004128
申请日：2000-06-23
IPC分类号： G01Q60/10 , G11C29/50 , G01R31/00 , G01R27/26
CPC分类号： G11C11/22 , B82Y10/00 , G11C29/50 , G11C2029/5002 , G11C2029/5006 , Y10S977/852
摘要： A ferroelectric film measuring device and a measuring method therefor, which are capable of measuring the transient current with high accuracy produced during the polarization reversal of a ferroelectric capacitor having a very small capacity. A pulse producer (10) produces a pulse signal, which is applied to the upper electrode (62) of a ferroelectric capacitor through a transmission line and a tip (50). The output current (iFE) from a lower electrode (64) produced at pulse application is converted into a voltage (V1) by a resistance element (30), amplified by a preamplifier (40), and delivered, the current (iFE) being measured on the basis of the output voltage (V0). A pulse having negative and positive amplitudes is applied to the upper electrode (62) continuously twice each time and the output current produced at each pulse application is measured. And the difference between the currents corresponding to the first and second pulses is found, thereby making it possible to eliminate the influences of charge current due to parasitic capacity such as in the transmission line, to extract only the polarization current due to polarization reversal of the ferroelectric substance, and to measure the properties of the ferroelectric film with high accuracy.
摘要翻译：一种铁电体膜测量装置及其测量方法，其能够在具有非常小的容量的铁电电容器的极化反转期间产生高精度的瞬态电流的测量。脉冲发生器（10）通过传输线和尖端（50）产生施加到铁电电容器的上电极（62）的脉冲信号。在脉冲施加时产生的来自下电极（64）的输出电流（iFE）由电阻元件（30）转换成电压（V1），由前置放大器（40）放大并传送，电流（iFE）为基于输出电压（V0）测量。每次连续施加两次具有负振幅和正振幅的脉冲，并测量每个脉冲施加时产生的输出电流。并且发现与第一和第二脉冲相对应的电流之间的差异，从而可以消除由于诸如传输线路之类的寄生电容引起的充电电流的影响，仅提取由于极化反转引起的极化电流铁电体物质，并且以高精度测量铁电体膜的性质。

32. 发明申请

WO98036418A1 METHOD FOR MINIMIZING THE ACCESS TIME FOR SEMICONDUCTOR MEMORIES 审中-公开
标题翻译：程序，以尽量减少半导体商店的访问时间
公开(公告)号：WO98036418A1
公开(公告)日：1998-08-20
申请号：PCT/DE1998/000290
申请日：1998-02-02
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C11/4074 , G11C29/50 , G11C29/56 , G11C11/407 , G11C29/00
CPC分类号： G11C29/028 , G11C5/145 , G11C11/401 , G11C11/4074 , G11C29/50 , G11C29/50012 , G11C2029/5004
摘要： The access times of semiconductor memories are subject to production-dependent fluctuations, even with identical technological parameters. These fluctuations lead to a certain amount of slow memory chips. By boosting the internal distribution voltage of the slower semiconductor memory by an amount dependent in each case on the semiconductor memory in question, the access time is reduced. The method is applied in semiconductor memories, in particular dynamic semiconductor memories.
摘要翻译：由于制造的原因，都受到半导体存储器波动的存取时间，导致一定量的低速存储芯片，并在同一工艺参数。的访问时间是通过取决于相应的半导体存储器量的量增加越慢半导体存储器的内部电源电压缩短。该方法是在半导体存储器中使用，特别是在动态半导体存储器。

33. 发明申请

WO1998014883A1 A METHOD AND APPARATUS FOR SAMPLING DATA FROM A MEMORY 审中-公开
标题翻译：用于从存储器中采集数据的方法和装置
公开(公告)号：WO1998014883A1
公开(公告)日：1998-04-09
申请号：PCT/US1997014022
申请日：1997-08-08
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MURDOCH, Robert, N. , WILLIAMS, Michael, W. , SADHASIVAN, Sathyamurthi
IPC分类号： G06F13/14
CPC分类号： G11C7/106 , G11C7/1024 , G11C7/1051 , G11C7/1078 , G11C8/18 , G11C11/401 , G11C29/50
摘要： Falling edges of a column address strobe (CAS) signal (109) are used to cause dynamic random access memories (DRAMs, 100) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches (102). A memory latch data (MLAD) signal (112) is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal.
摘要翻译：列地址选通（CAS）信号（109）的下降沿用于使动态随机存取存储器（DRAM，100）将与当前地址对应的数据驱动到耦合到一组锁存器（102）的输入端的数据总线上）。存储器锁存数据（MLAD）信号（112）用于使能该组锁存器。当MLAD信号被置位时，锁存器响应于CAS信号的下降沿在输入端锁存数据。当MLAD信号被断言时，锁存器不会响应CAS信号的下降沿在输入端锁存数据。

34. 发明申请

WO1997037357A1 CIRCUIT ARRANGEMENT WITH A TEST CIRCUIT 审中-公开
标题翻译：与测试电路电路
公开(公告)号：WO1997037357A1
公开(公告)日：1997-10-09
申请号：PCT/DE1997000623
申请日：1997-03-26
申请人： SIEMENS AKTIENGESELLSCHAFT , ZETTLER, Thomas , SOMMER, Diether , GEORGAKOS, Georg
发明人： SIEMENS AKTIENGESELLSCHAFT
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C16/04 , G11C29/50
摘要： The invention relates to a circuit arrangement with a predetermined number of group lines (WL0, ..., Wlm, BL0, ..., BLm) which are arranged at regular intervals adjacent each other on a semiconductor substrate (26) and to which a plurality of elementary electronic circuits (7) formed on the semiconductor substrate (26) and substantially identically are connected. A test circuit for checking the electronic operability of the elementary circuits (7) and/or the group lines (WL0, ..., Wlm, BL0, ..., BLm) is provided which is also integrated on the semiconductor substrate (26) of the circuit arrangement, has a switching device (30) which is associated with the group lines (WL0, ..., Wlm, BL0, ..., BLm) and is used to actuate at least one predetermined group line (W1n, BLn) by a first test signal. A further group line (W1n', Bln', n'=n-1, n'=n+1) arranged directly adjacent in relation to the predetermined group line (Wln, BLn) is actuated by a second test signal having a different test level in relation to the first test signal, and detection means (31) associated with the group lines (WL0, ..., Wlm, BL0, ..., BLm) is provided and determines an output signal derived from the group lines (W1n, BLn or W1n', BLn') which have received the first or second test signal.______________________
摘要翻译：本发明涉及一种电路装置具有彼此相邻地配置的基线（WL0，...，Wlm的，BL0，...，BLm的）的规则排列的半导体衬底（26）上的预定数量的在其上的多个所述半导体衬底上（26）和大致相同地形成，以彼此的电子基本电路（7）连接，其特征在于，一个测试电路，用于检查所述初级电路的电子功能能力（7）和/或组的行（WL0，...，Wlm的，BL0，...， BLM）被提供，类似地形成（集成电路装置的半导体基板26）上，一个（该基团线WL0，...，Wlm的，BL0，...，BLm的）与切换装置（30）相关联，借助该至少一个预定组线（WLN，BLn的）紧邻于第一测试信号和另一个，相对的预定组线（WLN，BLn的）排列的一组线（WLN“ BLN”，N‘= N-1，N’= N + 1）具有可装载的第二不同的具有测试电平的测试信号，相比于所述第一测试信号，并且将基线（WL0，...，提供Wlm的，BL0，...，BLm的）的检测装置（31相关联），其检测（从通过所述第一或第二测试信号线WLn基，BLn的或WLN“ BLn的”）衍生的输出信号采取行动。

35. 发明申请

WO1996032728A1 CIRCUIT FOR SRAM TEST MODE ISOLATED BITLINE MODULATION 审中-公开
标题翻译： SRAM测试模式隔离线调制电路
公开(公告)号：WO1996032728A1
公开(公告)日：1996-10-17
申请号：PCT/US1996003382
申请日：1996-03-12
申请人： MICRON TECHNOLOGY, INC.
发明人： MICRON TECHNOLOGY, INC. , MARR, Kenneth, W.
IPC分类号： G11C29/00
CPC分类号： G11C29/46 , G11C11/41 , G11C29/50 , G11C2029/5004
摘要： A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.
摘要翻译：电路和方法提供SRAM位线电压电平的隔离调制，以改进SRAM单元的电压突起保持测试。第一FET连接到Vcc，SRAM单元的位线负载门和测试模式操作控制逻辑。第二个FET连接到位线负载门，测试模式逻辑和SRAM器件的外部引脚。在测试模式操作期间，第一个FET将Vcc禁止位线，而第二个FET使得内部位线电压电平可以通过器件的外部引脚接收的电压来调制。位线电压电平的调制与诸如字线的外围电路的正常工作电压电平隔离。替代实施例提供了一个CMOS传输门来代替第二个FET。

36. 发明申请

WO9428549A3 ERASE AND PROGRAM VERIFICATION CIRCUIT FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的擦除和编程验证电路
公开(公告)号：WO9428549A3
公开(公告)日：1996-06-20
申请号：PCT/US9305135
申请日：1993-05-28
申请人： NIPPON KOKAN KK , MACRONIX INT CO LTD , LIN TIEN LER , YIU TOM DANG HSING , CHAO LIANG
发明人： LIN TIEN-LER , YIU TOM DANG-HSING , CHAO LIANG
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/28 , G11C16/34 , G11C29/50 , G11C
CPC分类号： G11C16/3445 , G06F2201/81 , G11C16/04 , G11C16/0491 , G11C16/28 , G11C16/3436 , G11C16/3459 , G11C29/028 , G11C29/50 , G11C2029/5004
摘要： For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells (10) and reference cells (23), and sense circuitry (27) responsive to addressed memory cells (10) and the reference cells (23), and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells (10) is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory (10) and reference cells (23) is equivalent to adjusting the sense ratio.

37. 发明申请

WO9608822A2 SENSE AMPLIFIER FOR NON-VOLATILE SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于非易失性半导体存储器的感测放大器
公开(公告)号：WO9608822A2
公开(公告)日：1996-03-21
申请号：PCT/IB9500702
申请日：1995-08-28
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： TRODDEN THOMAS JOHN
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , G11C29/38 , G11C29/50 , G11C7/06
CPC分类号： G11C16/28 , G11C16/04 , G11C29/38 , G11C29/50
摘要： A non-volatile semiconductor memory utilizes a sense amplifier to compare the logic state of a memory cell to that of a reference cell. Loads that supply currents to the memory cell and the reference cell form a current mirror, whose amplification factor is controllably dependent on the level of the supply voltage. This configuration renders the sensitivity of the amplifier higher with a lower supply voltage than with a higher supply voltage.
摘要翻译：非易失性半导体存储器利用读出放大器将存储器单元的逻辑状态与参考单元的逻辑状态进行比较。向存储器单元和参考单元提供电流的负载形成电流镜，其放大系数可控地依赖于电源电压的电平。该配置使得放大器的灵敏度随着较低的电源电压而高于较高的电源电压。

38. 发明申请

WO1982002792A1 SEMICONDUCTOR MEMORY CELL MARGIN TEST CIRCUIT 审中-公开
标题翻译：半导体存储器存储器测试电路
公开(公告)号：WO1982002792A1
公开(公告)日：1982-08-19
申请号：PCT/US1981000136
申请日：1981-02-02
申请人： MOSTEK CORP , OTOOLE JAMES E , PROEBSTING ROBERT J
发明人： MOSTEK CORP
IPC分类号： G11C11/40
CPC分类号： G11C29/50 , G06F2201/81
摘要： A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V u *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V u *) is the semiconductor memory circuit main supply source (V u) in normal operation but can be forced to a different voltage during the margin test.
摘要翻译：为具有多个存储单元（16）的半导体存储器电路提供了裕量测试电路（10）。一行单元（16）中的每个存储单元（16）互连到字线（14）。边缘检验电路（10）还包括行解码器/驱动器（12），其接收用于改变存储在存储单元（16）内的信号电平的可变电压（V uC> u *），从而确定边际电压电平存储单元（16）将保持信号电平的存储。可变电压（V ucc> u *）是正常操作中的半导体存储器电路主电源（V ucc> u），但是在裕量测试期间可以被强制为不同的电压。

39. 发明申请

WO2018063570A1 TECHNOLOGIES FOR PHYSICALLY UNCLONABLE FUNCTIONS WITH MAGNETIC TUNNEL JUNCTIONS 审中-公开
标题翻译：具有磁性隧道接头的物理无限功能技术
公开(公告)号：WO2018063570A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/047538
申请日：2017-08-18
申请人： INTEL CORPORATION
发明人： TOMISHIMA, Shigeki
IPC分类号： G11C11/16 , H04L9/08
CPC分类号： H04L9/0894 , G09C1/00 , G11C7/20 , G11C7/24 , G11C8/12 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C29/50 , G11C2029/4402 , G11C2029/5002 , H04L9/0861 , H04L9/0866 , H04L9/14 , H04L9/3278
摘要： Technologies for a physically unclonable function with magnetic tunnel junctions (MTJs) is disclosed. An MTJ may have a fixed layer and a free layer. The MTJ may have two stable states: one in which the orientation of the magnetization of the fixed layer is parallel to the free layer, and one in which it is antiparallel. If the magnetic tunnel junction has a voltage-controlled magnetic anisotropy, when a voltage is applied across the MTJ, the orientation of the magnetic field of the free layer of the MTJ may be perpendicular to that of the fixed layer. When the voltage is removed, the orientation of the magnetization of the free layer relaxes back to one of the two stable configurations. Which state the free layer ends up at may not be predictable at the time of manufacture, but may be repeatable due to influences from variations in the manufacturing process.
摘要翻译：公开了具有磁隧道结（MTJ）的物理不可克隆功能的技术。一个MTJ可能有一个固定层和一个自由层。 MTJ可以具有两个稳定状态：其中固定层的磁化方向平行于自由层，并且其中反平行的一个方向。如果磁隧道结具有电压控制的磁各向异性，则当在MTJ上施加电压时，MTJ的自由层的磁场的取向可以与固定层的磁场的取向垂直。当电压被移除时，自由层的磁化方向松弛回两种稳定结构之一。自由层的最终状态在制造时可能是不可预测的，但由于制造过程中的变化的影响可能是可重复的。

40. 发明申请

WO2016195719A1 READ CIRCUITRY FOR ELECTROSTATIC DISCHARGE SWITCHING MEMRISTIVE ELEMENT 审中-公开
标题翻译：静电放电开关元件读取电路
公开(公告)号：WO2016195719A1
公开(公告)日：2016-12-08
申请号：PCT/US2015/034539
申请日：2015-06-05
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： BUCHANAN, Brent , GE, Ning , AULETTA, Richard James
IPC分类号： G11C11/15 , G11C13/00
CPC分类号： G11C7/24 , G11C5/06 , G11C13/0007 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C29/50 , G11C2013/0045 , G11C2013/0054 , G11C2013/0078 , G11C2029/5002 , H02H1/0061 , H02H9/046
摘要： In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.
摘要翻译：在本文提供的示例中，装置具有耦合到集成电路的引脚的忆阻元件，其中忆阻元件从第一电阻值范围内的第一电阻切换到响应中的第二电阻值范围内的第二电阻到引脚上的静电放电（ESD）事件。该装置还具有耦合到忆阻元件的读取电路，以确定忆阻元件的电阻是否在电阻值的第一或第二范围内，其中读取电路包括第一晶体管。此外，读取电路和忆阻元件之间的耦合不包括用于从ESD事件到第一晶体管的栅极端子的电流的直接路径。

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