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31. 发明申请

WO2023027710A1 ENHANCED COOLING PACKAGE FOR IMPROVED THERMAL MANAGEMENT FOR ELECTRICAL COMPONENTS 审中-公开
公开(公告)号：WO2023027710A1
公开(公告)日：2023-03-02
申请号：PCT/US2021/047758
申请日：2021-08-26
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： DING, Huiying , JIN, Longnan , BAI, Junkai , CHIN, Jui Sen
IPC分类号： H01L23/367 , H01L21/60 , H01L21/52 , H01L23/34 , H01L23/48 , H05K1/02
摘要： A electrical component package includes a folded heat sink for increased heat dissipation. The internal components of the package include an electrical component, a lead frame, a conductive clip, and terminal leads, which are electrically and mechanically interconnected. A packaging material is utilized to form a mold for encapsulating the internal components, the mold including a portion that is recessed. A heat sink is provided for heat dissipation and includes a first planar portion that extends from the lead frame, a second planar portion that is in spaced relation from the recessed portion of the mold, and a fold portion that is integral with and extends between the first and second planar portions.

32. 发明申请

WO2015006028A1 GALLIUM NITRIDE POWER SEMICONDUCTOR DEVICE HAVING A VERTICAL STRUCTURE 审中-公开
标题翻译：具有垂直结构的氮化镓电力半导体器件
公开(公告)号：WO2015006028A1
公开(公告)日：2015-01-15
申请号：PCT/US2014/042855
申请日：2014-06-18
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： CHEN, Max SK , LIN, Yih-Yin
IPC分类号： H01L29/861 , H01L29/78
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/41 , H01L29/4175 , H01L29/66469 , H01L29/7786 , H01L29/7787 , H01L29/7788 , H01L29/872
摘要： A semiconductor device includes a substrate having first and second sides and a first active layer disposed over the first side of the substrate. A second active layer is disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. At least one trench extends through the first and second active layers and the two-dimensional electron gas layer and into the substrate. A conductive material lines the trench. A first electrode is disposed on the second active layer and a second electrode is disposed on the second side of the substrate.
摘要翻译：半导体器件包括具有第一和第二侧的衬底和设置在衬底的第一侧上的第一有源层。第二活性层设置在第一活性层上。第二有源层具有比第一有源层更高的带隙，使得在第一有源层和第二有源层之间产生二维电子气层。至少一个沟槽延伸穿过第一和第二有源层和二维电子气层并进入衬底。导电材料对沟槽进行排列。第一电极设置在第二有源层上，第二电极设置在衬底的第二侧上。

33. 发明申请

WO2014110563A1 ELECTRICAL PRESS-FIT PIN FOR A SEMICONDUCTOR MODULE 审中-公开
标题翻译：用于半导体模块的电压引线
公开(公告)号：WO2014110563A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/011454
申请日：2014-01-14
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： MATTIUZZO, Emilio
IPC分类号： H01R12/51 , H01R12/55
CPC分类号： H01R13/415 , H01R12/585 , H01R43/26 , Y10T29/49147
摘要： An electrical module includes a housing, at least one electrical component mounted within the housing and an electrical press-fit contact. The electrical press-fit contact is located in part within the housing and has a press fit portion and a stop portion at its distal end and a mounting portion at its proximal end. The mounting portion is electrically coupled to the electrical component. The press-fit portion is located exterior of the housing such that the stop portion is able to block movement of the press-fit section into the housing when a press-in force is introduced onto the press-in contact to press the press-fit contact into the housing.
摘要翻译：电气模块包括壳体，安装在壳体内的至少一个电气部件和电压配合触点。电压配合触头部分地位于壳体内，并且在其远端具有压配合部分和止动部分及其近端处的安装部分。安装部分电耦合到电气部件。压配合部分位于壳体的外部，使得止挡部分能够阻止压配合部分进入壳体的移动，当压入力被引入到压入接触件中以压配合联系到房屋。

34. 发明申请

WO2014074120A1 AXIAL SEMICONDUCTOR PACKAGE 审中-公开
标题翻译：轴向半导体封装
公开(公告)号：WO2014074120A1
公开(公告)日：2014-05-15
申请号：PCT/US2012/070402
申请日：2012-12-18
申请人： VISHAY GENERAL SEMICONDUCTOR LLC
发明人： CHIANG, Wan-lan , PENG, Chih-ping , DING, Hui-ying
IPC分类号： H01L23/498 , H01L23/48
CPC分类号： H01L21/56 , H01L23/051 , H01L23/3107 , H01L24/01 , H01L24/33 , H01L2924/12042 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： An axially-mountable device includes a semiconductor chip comprising lower and upper electrical contacts. A lower die pad is electrically and mechanically connected to the lower electrical contact of the chip. An upper die pad is electrically and mechanically connected to the upper electrical contact of the chip. A first axially extending electrical lead is electrically and mechanically connected to the upper die pad and extends in a first axial direction. A second axially extending electrical lead is electrically and mechanically connected to the lower die pad and extends in a second axial direction that is opposite to the first axial direction. Packaging material encapsulates the semiconductor chip, the upper and lower die pads and a portion of the first and second axially extending leads. The first and second leads extend from the packaging material and are adapted to allow the device to be axially-mounted with another electrical component.
摘要翻译：可轴向安装的装置包括包括下电极和上电触点的半导体芯片。下芯片焊盘电连接和机械连接到芯片的下电触头。上芯片焊盘电连接和机械连接到芯片的上电触头。第一轴向延伸的电引线电连接并机械地连接到上模焊盘并且在第一轴向方向上延伸。第二轴向延伸的电引线电连接和机械连接到下模垫，并在与第一轴向方向相反的第二轴向方向上延伸。包装材料包封半导体芯片，上下模片和第一和第二轴向延伸引线的一部分。第一和第二引线从包装材料延伸并且适于允许装置与另一电气部件轴向安装。

35. 发明申请

WO2009049188A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：WO2009049188A1
公开(公告)日：2009-04-16
申请号：PCT/US2008/079552
申请日：2008-10-10
申请人： VISHAY GENERAL SEMICONDUCTOR, LLC , CHOU, Ta-Te , TIAN, Yong-Qi , LI, Xian
发明人： CHOU, Ta-Te , TIAN, Yong-Qi , LI, Xian
IPC分类号： H01L23/24
CPC分类号： H01L23/34 , H01L23/3107 , H01L23/3672 , H01L23/4093 , H01L23/49586 , H01L2224/32245 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
摘要翻译：提供可安装到基板的半导体器件。该器件包括具有至少一个半导体管芯，导电附着区域和其中嵌入半导体管芯的封装材料和接触管芯的导电附着区域的第一部分的半导体封装。金属外壳包围嵌入式半导体管芯和导电附接区域的第一部分。

36. 发明申请

WO2009009576A1 SUBASSEMBLY THAT INCLUDES A POWER SEMICONDUCTOR DIE AND A HEAT SINK AND METHOD OF FORMING SAME 审中-公开
标题翻译：包括功率半导体芯片和散热片及其形成方法
公开(公告)号：WO2009009576A1
公开(公告)日：2009-01-15
申请号：PCT/US2008/069501
申请日：2008-07-09
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , CHIANG, Wan-Lan , LIN, Kuang, Hann , PENG, Chih-Ping
发明人： CHIANG, Wan-Lan , LIN, Kuang, Hann , PENG, Chih-Ping
IPC分类号： H01L21/00
CPC分类号： H01L23/367 , H01L23/4093 , H01L23/4334 , H01L23/49562 , H01L2224/26175 , H01L2224/291 , H01L2224/32245 , H01L2224/33181 , H01L2924/10253 , H01L2924/12044 , H01L2924/00 , H01L2924/014
摘要： A semiconductor assembly includes a first subassembly comprising a heat sink and a first patterned polymer layer disposed on a surface of the heat sink to define an exposed portion of the first surface. The exposed portion of the first surface extends radially inward along the heat sink surface from the first layer. The subassembly also includes a second patterned polymer layer disposed on a radially outer portion of the first patterned polymer layer. The first and second layers define a cell for accommodating a power semiconductor die. Solder material is disposed on the exposed portion of the heat sink surface and in the cell. A power semiconductor die is located within the cell on a radially inward portion of the first layer and thermally coupled to the heat sink by the solder material.
摘要翻译：半导体组件包括第一子组件，其包括散热器和设置在散热器的表面上以限定第一表面的暴露部分的第一图案化聚合物层。第一表面的暴露部分沿着散热表面从第一层径向向内延伸。子组件还包括设置在第一图案化聚合物层的径向外部部分上的第二图案化聚合物层。第一和第二层限定用于容纳功率半导体管芯的电池。焊料设置在散热器表面的暴露部分和电池中。功率半导体管芯位于第一层的径向向内部分内的单元内，并通过焊料材料热耦合到散热器。

37. 发明申请

WO2008048384A2 POTTED INTEGRATED CIRCUIT DEVICE WITH ALUMINUM CASE 审中-公开
标题翻译：带铝壳的集成电路集成电路装置
公开(公告)号：WO2008048384A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/017765
申请日：2007-08-10
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , CHOU, Peter , TIAN, Lucy , FU, Ivan , LI, Samuel , CHOU, M.l.
发明人： CHOU, Peter , TIAN, Lucy , FU, Ivan , LI, Samuel , CHOU, M.l.
IPC分类号： H01L23/34
CPC分类号： H01L23/24 , H01L23/49562 , H01L24/36 , H01L24/40 , H01L2224/40095 , H01L2224/40245 , H01L2224/83801 , H01L2924/14 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
摘要翻译：集成电路器件包括管芯，引线和布置成促进管芯和引线之间的电连通的导电结构。该装置还包括封装材料，其中嵌入导电结构，管芯和引线的至少一部分。导电壳体包封灌封材料并形成装置的外部包装。在制造期间，可以在将灌封材料布置在壳体中之前或之后将导电结构，模具和引线的至少一部分布置在导电壳体内。当集成电路器件工作时，通过由导电结构，灌注材料和导电外壳形成的热传导路径，可以从管芯移除热量。

38. 发明申请

WO2008021272A2 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：WO2008021272A2
公开(公告)日：2008-02-21
申请号：PCT/US2007/017849
申请日：2007-08-10
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , CHOU, Ta-te , ZHANG, Xiong-jie , LI, Xian , FU, Hai , TIAN, Yong-qi
发明人： CHOU, Ta-te , ZHANG, Xiong-jie , LI, Xian , FU, Hai , TIAN, Yong-qi
IPC分类号： H01L21/00 , H01L23/34
CPC分类号： H01L23/49575 , H01L23/49562 , H01L23/49568 , H01L23/49586 , H01L2224/32245 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.
摘要翻译：提供可安装到基板的半导体器件。该器件包括半导体管芯和具有第一附接表面和第二附接表面的导电附接区域。第一附接表面布置成与半导体管芯电连通。中间层材料形成在导电性附着区域的第二附着面上。中间层材料是导热的介电材料。壳体至少部分地包围半导体管芯和中间层材料。

39. 发明申请

WO2008021221A3 LOW VOLTAGE TRANSIENT VOLTAGE SUPPRESSOR WITH REDUCED BREAKDOWN VOLTAGE 审中-公开
公开(公告)号：WO2008021221A3
公开(公告)日：2008-02-21
申请号：PCT/US2007/017770
申请日：2007-08-10
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , DAI, Sheng-Huei , KING, Ya-Chin , WANG, Hai-Ning , CHIANG, Ming-Tai
发明人： DAI, Sheng-Huei , KING, Ya-Chin , WANG, Hai-Ning , CHIANG, Ming-Tai
IPC分类号： H01L29/06 , H01L21/20
摘要： A semiconductor junction device includes a substrate 202 of low resistivity semiconductor material having a preselected polarity. A tapered recess 210 extends into the substrate 202 and tapers inward as it extends downward from an upper surface of the substrate 202. A semiconductor layer (N+ POLY) is disposed within the recess 210 and extends above the upper surface of the substrate 202. The semiconductor layer (N+ POLY) has a polarity opposite from that of the substrate 202. A metal layer 212 overlies the semiconductor layer (N+ POLY).

40. 发明申请

WO2006104926A3 ASYMMETRIC BIDIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR AND METHOD OF FORMING SAME 审中-公开
公开(公告)号：WO2006104926A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/010884
申请日：2006-03-24
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , KUNG, Pu-ju , HUANG, Chun-jen , KAO, Lung-ching , PENG, Hung-jieu
发明人： KUNG, Pu-ju , HUANG, Chun-jen , KAO, Lung-ching , PENG, Hung-jieu
IPC分类号： H01L21/20 , H01L21/22 , H01G9/20
摘要： A bi-directional transient voltage suppression device and a method of making same is provided. The method begins by providing a semiconductor substrate of a first conductivity type, and depositing a first epitaxial layer of a second conductivity type opposite the first conductivity type on the substrate. The substrate and the first epitaxial layer form a first p-n junction. A second epitaxial layer having the second conductivity type is deposited on the first epitaxial layer. The second epitaxial layer has a higher dopant concentration than the first epitaxial layer. A third layer having the first conductivity type is formed on the second epitaxial layer. The second epitaxial layer and the third layer form a second p-n junction.

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