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21. 发明申请

WO2005062378A1 PILLAR CELL FLASH MEMORY TECHNOLOGY 审中-公开
标题翻译：支柱电池闪存存储技术
公开(公告)号：WO2005062378A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/040324
申请日：2004-12-01
申请人： SANDISK CORPORATION , MOKHLESI, Nima , LUTZE, Jeffrey W.
发明人： MOKHLESI, Nima , LUTZE, Jeffrey W.
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , G11C16/0458 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： An array of a pillar-type nonvolatile memory cells (803) has each memory cell isolated from adjacent memory cells by a trench (810). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer (815), polysilicon floating gate layer (819), ONO or oxide layer (822), polysilicon control gate layer (825). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle (843) to the floating gate (819).
摘要翻译：柱状非易失性存储单元（803）的阵列具有通过沟槽（810）与相邻存储单元隔离的每个存储单元。每个存储单元由衬底上的堆叠处理层形成：隧道氧化物层（815），多晶硅浮动栅极层（819），ONO或氧化物层（822），多晶硅控制栅极层（825）。这个过程的很多方面都是自相矛盾的。这些存储单元的阵列将需要较少的分割。此外，存储单元具有增强的编程特性，因为电子被引导到浮动栅极（819）的正常或几乎正常的角度（843）。

22. 发明申请

WO2011031660A2 IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中识别风险数据
公开(公告)号：WO2011031660A2
公开(公告)日：2011-03-17
申请号：PCT/US2010/047951
申请日：2010-09-07
申请人： SANDISK CORPORATION , PEI, Gen , GU, Lanlan , MOKHLESI, Nima , ALROD, Idan , SHARON, Eran , AFRIAT, Itshak
发明人： PEI, Gen , GU, Lanlan , MOKHLESI, Nima , ALROD, Idan , SHARON, Eran , AFRIAT, Itshak
IPC分类号： G11C16/34
CPC分类号： G11C16/3418 , G06F11/1072
摘要： The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use.
摘要翻译：非易失性存储系统基于性能数据预测哪些块（或其他存储单元）将变坏。预测为坏的那些块中的用户数据可以被重新编程到其他块，并且预测为坏的块可以被进一步使用。

23. 发明申请

WO2008154229A1 NON-VOLATILE MEMORY AND METHOD FOR IMPROVED SENSING HAVING BIT-LINE LOCKOUT CONTROL 审中-公开
标题翻译：非易失性存储器和具有位线锁定控制的改进感测方法
公开(公告)号：WO2008154229A1
公开(公告)日：2008-12-18
申请号：PCT/US2008/065681
申请日：2008-06-03
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/26 , G11C11/56
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/5634
摘要： In sensing a group of cells in a multi-state nonvolatile memory, multiple sensing cycles relative to different demarcation threshold levels are needed to resolve all possible multiple memory states. Each sensing cycle has a sensing pass. It may also include a pre-sensing pass or sub-cycle to identify the cells whose threshold voltages are below the demarcation threshold level currently being sensed relative to. These are higher current cells which can be turned off to achieve power-saving and reduced source bias errors. The cells are turned off by having their associated bit lines locked out to ground. A repeat sensing pass will then produced more accurate results. Circuitry and methods are provided to selectively enable or disable bit-line lockouts and pre-sensing in order to improving performance while ensuring the sensing operation does not consume more than a maximum current level.
摘要翻译：在感测多状态非易失性存储器中的一组单元时，需要相对于不同分界阈值电平的多个感测周期来解决所有可能的多个存储器状态。每个感测周期都有一个感测通道。它还可以包括预感测通过或子周期，以识别其阈值电压低于当前正在被感测的分界阈值水平的单元。这些是更高的电流单元，可以关闭以实现省电和减少源偏置误差。通过将它们的相关位线锁定到地来关闭电池。然后，重复感应通过将产生更准确的结果。提供电路和方法来选择性地启用或禁用位线锁定和预感测，以便提高性能，同时确保感测操作不消耗超过最大电流电平。

24. 发明申请

WO2008103586A1 DYNAMIC VERIFY BASED ON THRESHOLD VOLTAGE DISTRIBUTION 审中-公开
标题翻译：基于阈值电压分配的动态验证
公开(公告)号：WO2008103586A1
公开(公告)日：2008-08-28
申请号：PCT/US2008/053858
申请日：2008-02-13
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/344
摘要： After erasing a plurality of non-volatile storage elements, a soft programming process is performed to tighten the erase threshold distribution for the non-volatile storage elements. During the soft programming process, the system identifies the number of programming pulses needed for a first set of the non- volatile storage elements to complete the soft programming and the number of programming pulses needed for the all but a last set of non-volatile storage elements to complete soft programming. These two numbers are used to characterize the threshold distribution of the non-volatile storage elements. This characterization of the threshold distribution and the program pulse step size are used to limit the number of verify pulses used during subsequent programming.
摘要翻译：在擦除多个非易失性存储元件之后，执行软编程处理以紧固非易失性存储元件的擦除阈值分布。在软编程过程期间，系统识别用于完成软编程的第一组非易失性存储元件所需的编程脉冲的数量以及除最后一组非易失性存储器之外的所有数据所需的编程脉冲数元素完成软编程。这两个数字用于表征非易失性存储元件的阈值分布。门限分布和程序脉冲步长的这种表征用于限制在后续编程期间使用的验证脉冲的数量。

25. 发明申请

WO2008083137A1 READING OF A NONVOLATILE MEMORY CELL BY TAKING ACCOUNT OF THE STORED STATE OF A NEIGHBORING MEMORY CELL 审中-公开
标题翻译：通过记录邻近存储单元的存储状态来读取非易失性存储单元
公开(公告)号：WO2008083137A1
公开(公告)日：2008-07-10
申请号：PCT/US2007/088787
申请日：2007-12-24
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3418 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/3427 , G11C16/3454 , G11C29/52
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.
摘要翻译：由于存储在相邻浮动栅极（或其他电荷存储元件）中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的浮动栅极（或其他电荷存储元件）上的视在电荷的变化，。为了解决这种耦合，对于目标存储器单元的读取处理将向邻近的存储器单元（或其他存储单元）提供补偿，以便减少相邻存储单元对目标存储器单元具有的耦合效应。所施加的补偿基于相邻存储单元的条件。为了应用正确的补偿，读取过程将至少部分地将相邻存储器单元的读取操作与目标存储器单元的读取操作混合。

26. 发明申请

WO2008042605A1 REVERSE READING IN NON-VOLATILE MEMORY WITH COMPENSATION FOR COUPLING 审中-公开
标题翻译：非易失性存储器中的反向读取与补偿的补偿
公开(公告)号：WO2008042605A1
公开(公告)日：2008-04-10
申请号：PCT/US2007/078950
申请日：2007-09-19
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/26 , G11C16/10 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418
摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non- volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.
摘要翻译：由于基于存储在相邻（或其它）电荷存储区域中的电荷的电场耦合，可能会发生由非易失性存储单元中的诸如浮动栅极之类的电荷存储区域存储的视在电荷的变化。尽管不是排他地，但是在选择的存储单元之后对相邻存储单元进行编程的情况下，效果最明显。为了考虑视在电荷的偏移，基于由其他字线的存储元件存储的电荷来读取所选字线的存储元件时，应用一个或多个补偿。高效补偿技术由存储单元的反向读取块（或其部分）提供。通过以相反的编程方向读取，在读取所选单元格期间应用（或选择结果）所需的信息在相邻字线的实际读取操作期间被确定，而不是专用于读取操作来确定信息。

27. 发明申请

WO2007103038A1 READ OPERATION FOR NON-VOLATILE STORAGE WITH COMPENSATION FOR FLOATING GATE COUPLING 审中-公开
标题翻译：阅读操作非浮动存储与浮动闸门耦合补偿
公开(公告)号：WO2007103038A1
公开(公告)日：2007-09-13
申请号：PCT/US2007/004967
申请日：2007-02-27
申请人： SANDISK CORPORATION , MOKHLESI, Nima
发明人： MOKHLESI, Nima
IPC分类号： G11C16/26
CPC分类号： G11C16/26 , G11C16/3418
摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell. For this, a read voltage is applied to the word line of the selected memory cell, a second pass voltage is applied to the word line of the memory cell adjacent to the selected memory cell and a first pass voltage is applied to the further word lines. Before reading the selected memory cell, the state of the adjacent memory cell is read and, according to this state, the second pass voltage is set.
摘要翻译：存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合）。在不同时间编程的相邻存储器单元组之间最明显地出现该问题。为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元的耦合效应。为此，将读取电压施加到所选存储单元的字线，将第二通过电压施加到与所选择的存储单元相邻的存储单元的字线，并且第一通过电压被施加到另外的字线。在读取所选择的存储单元之前，读取相邻存储单元的状态，根据该状态设定第二通过电压。

28. 发明申请

WO2007019010A1 SYSTEM AND METHOD FOR PROGRAMMING CELLS IN NON-VOLATILE INTEGRATED MEMORY DEVICES 审中-公开
标题翻译：用于在非易失性集成存储器件中编程细胞的系统和方法
公开(公告)号：WO2007019010A1
公开(公告)日：2007-02-15
申请号：PCT/US2006/028278
申请日：2006-07-19
申请人： SANDISK CORPORATION , MOKHLESI, Nima , GUTERMAN, Daniel, C.
发明人： MOKHLESI, Nima , GUTERMAN, Daniel, C.
IPC分类号： G11C11/56
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5671 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C2211/5621
摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.
摘要翻译：提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

29. 发明申请

WO2005112036A1 BITUNE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY 审中-公开
标题翻译：双管齐下的非易失性存储器程序控制方法
公开(公告)号：WO2005112036A1
公开(公告)日：2005-11-24
申请号：PCT/US2005/013366
申请日：2005-04-20
申请人： SANDISK CORPORATION , GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
发明人： GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
摘要翻译：在用于编程非易失性存储器的系统中，公开了用于以更高的精度和合理的程序时间进行编程的技术。在一个实施例中，第一电压被施加到用于第一非易失性存储元件的位线，以便禁止第一非易失性存储元件。第一编程电压被施加到第一非易失性存储元件。例如，将编程脉冲施加到第一非易失性存储元件的控制栅极。在编程脉冲期间，位线从所述第一电压改变到第二电压，其中第二电压允许第一非易失性存储元件被编程。

30. 发明申请

WO2005073980A1 CHARGE PACKET METERING FOR COARSE /FINE PROGRAMMING OF NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的精细/精细编程的充值分组计量
公开(公告)号：WO2005073980A1
公开(公告)日：2005-08-11
申请号：PCT/US2005/002143
申请日：2005-01-25
申请人： SANDISK CORPORATION , GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
发明人： GUTERMAN, Daniel, C. , MOKHLESI, Nima , FONG, Yupin
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

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