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21. 发明申请

WO1993005429A1 OPTICAL DEVICE 审中-公开
标题翻译：光学装置
公开(公告)号：WO1993005429A1
公开(公告)日：1993-03-18
申请号：PCT/JP1992001138
申请日：1992-09-04
申请人： FUJITSU LIMITED , FUKUSHIMA, Nobuhiro
发明人： FUJITSU LIMITED
IPC分类号： G02B27/28
CPC分类号： G02B6/2746 , G02B5/3083 , G02B6/4209 , G02B27/283 , G02F1/093 , G02F2203/06
摘要： An optical device for connecting first and second optical fibers through an optical path disposed between them, which has at least two functions including the function of an optical isolator. Parallel beams emitted from an excitation end of the first optical fiber (1) and collimated by a lens (3) pass sequentially through a birefrigence device (4), a magneto-optical device (5) and a birefrigence device (6) in order named, are converged by a lens (7) and are incident into the second optical fiber from its excitation end. However, the beam from the second optical fiber does not couple with the first optical fiber (1). The beam from an excitation port (8) couples with the first optical fiber. This optical device is suitable for an optical amplification system and a bidirectional optical transmission system.

22. 发明申请

WO1993004431A1 BUFFER MEMORY CONTROL SYSTEM 审中-公开
标题翻译：缓冲存储控制系统
公开(公告)号：WO1993004431A1
公开(公告)日：1993-03-04
申请号：PCT/JP1992001035
申请日：1992-08-13
申请人： FUJITSU LIMITED , MORIOKA, Tetsuya
发明人： FUJITSU LIMITED
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/1054
摘要： A system for controlling buffer memory using a part of a page address portion of a logical address and a part of an inside-page address portion as a line address, the system being provided with a TAG1 portion (13, 17) of each of a plurality of pipelines (IF, OP) disposed inside a CPU (1) in order to retrieve hit/mistake by the use of the part of the page address portion of the logical address and the part of the inside-page address as a basic line address, a DATA portion (14, 18) for holding data when each of the TAG1 portions is retrieved and hit by the basic line address, and TAG2 portions (21, 22) disposed inside a MCU (2) in order to retrieve hit/mistake by the use of an agreement line address obtained by changing a variable portion of the basic line address when the result proves mistake by the use of the basic line address. The TAG1 unit is retrieved by the use of only the basic line address at the time of data access, and when the result proves hit, access is made to the DATA unit. When the result proves mistake, on the other hand, the TAG2 unit is retrieved by the use of the basic line address and the agreement line address. When the result provides hit at this time, nullification of the DATA unit, move-out and nullification, and if necessary, activation of move-in, are made.
摘要翻译：一种用于使用逻辑地址的页面地址部分的一部分和内部页面地址部分的一部分作为行地址来控制缓冲存储器的系统，该系统被提供有一个TAG1部分（13,17）多个管道（IF，OP）设置在CPU（1）内，以便通过使用逻辑地址的页面地址部分的一部分和内部页面地址的一部分作为基本行来检索命中/错误地址，用于当每个TAG1部分被基本行地址检索和命中时保存数据的DATA部分（14,18）以及设置在MCU（2）内的TAG2部分（21,22），以便检索命中/ 通过使用通过使用基本行地址来证明错误的基本行地址的可变部分而获得的协议行地址的错误。通过在数据访问时仅使用基本行地址来检索TAG1单元，并且当结果被命中时，对DATA单元进行访问。另一方面，当结果证明错误时，通过使用基本行地址和协议行地址来检索TAG2单元。当结果在此时提供命中时，数据单元的无效，移出和无效，并且如果需要，进行移入的激活。

23. 发明申请

WO1993002485A1 MICROSTRIP LINE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译： MICROSTRIP LINE及其制造方法
公开(公告)号：WO1993002485A1
公开(公告)日：1993-02-04
申请号：PCT/JP1992000913
申请日：1992-07-17
申请人： FUJITSU LIMITED , TOZAWA, Norio
发明人： FUJITSU LIMITED
IPC分类号： H01P03/08
CPC分类号： H01P3/081 , H05K1/0237 , H05K1/0265 , H05K3/244 , H05K3/4015 , H05K2201/098 , H05K2201/1028
摘要： A microstrip line capable of feeding a large DC current, in spite of maintaining a high characteristic impedance. The microstrip line is provided with a dielectric base (10), an earthing conductor (12), a conductor strip (14), and an upper conductor part (16). The upper conductor part (16) is provided nearly on the central line of the conductor strip (14), and has a section which is thick in a vertical direction and whose width w1 of the lower base (16a) is narrower than the width W of the conductor strip (14) and respective width w2 from the base (16a) to its opposite side (16b) are nearly equal to the width w1 of the base (16a) or become larger than the width w1 at upper parts. The upper conductor part (16) of such sectional shape is formed by welding onto the conductor strip (14) a linear member made of gold, silver or copper whose section is shaped so through etching, or by depositing on the conductor strip (14) gold, silver or copper through plating.
摘要翻译：尽管维持高的特性阻抗，但是能够馈送大直流电流的微带线。微带线设置有电介质基底（10），接地导体（12），导体条（14）和上导体部分（16）。上导体部（16）大致设置在导体条（14）的中心线上，具有在垂直方向上较厚的部分，下基板（16a）的宽度w1比宽度W窄的导体条（14）的宽度w2和从基部（16a）到其相对侧（16b）的宽度w2几乎等于基部（16a）的宽度w1或变得大于上部的宽度w1。这种截面形状的上导体部分（16）通过在导体条（14）上焊接由金，银或铜制成的线状部件形成，其截面通过蚀刻成形，或通过沉积在导体条（14）上而形成，金，银或铜通过电镀。

24. 发明申请

WO1992022972A1 SYSTEM FOR TRANSFERRING DISCRIMINATIVE INFORMATION OF PACKET ROUTE 审中-公开
标题翻译：传送分组路由的辨别信息的系统
公开(公告)号：WO1992022972A1
公开(公告)日：1992-12-23
申请号：PCT/JP1992000772
申请日：1992-06-17
申请人： FUJITSU LIMITED , OGURA, Takao , AMEMIYA, Shigeo , TEZUKA, Koji , CHUJO, Takafumi
发明人： FUJITSU LIMITED
IPC分类号： H04L12/56
CPC分类号： H04L45/00
摘要： On a transmission side, provided is a means (2) which converts the discriminative information data on packet routes into the information of a bit map, the address of whose individual bit corresponds to the discriminative information on the packet routes. On a reception side provided is a means (5) which converts inversely, the information of the bit map, which is concerned with the discriminative information data on the packet routes, into the discriminative information data on the packet routes. Alternatively, further, on the transmission side, provided are means (8, 10) for inquiring the forefront and last value of the transmitted discriminative information data on a packet route respectively. Also, provided is a means (9) for converting, the discriminative information data on the packet route between the forefront and last value, into the information of the bit map. In this case, on the reception side, provided are means (13, 14) for converting, the information of the bit map, which is concerned with the discriminative information data on the packet route between the forefront and last value, into the original discriminative information data on the packet route. Further, determined is the discriminative information on the forefront packet route to be preset newly, according to the discriminative information on the idle packet route in a discriminative information table, which is concerned with the packet routes outputted from transmission side nodes. Then, the discriminative information about this forefront and other packet routes is transmitted. On the reception side, from the transmitted information, referring to a discriminative information table, which is concerned with the packet routes inputted to reception side nodes, the discriminative information on the new packet route is recognized.

25. 发明申请

WO1992022125A1 ELECTROSTATIC ACTUATOR AND CONTROLLING METHOD THEREOF 审中-公开
标题翻译：静电致动器及其控制方法
公开(公告)号：WO1992022125A1
公开(公告)日：1992-12-10
申请号：PCT/JP1992000683
申请日：1992-05-27
申请人： FUJITSU LIMITED , HIGUCHI, Toshiro , EGAWA, Saku , NIINO, Toshiki , NATORI, Katsuhide , TABATA, Fumio
发明人： FUJITSU LIMITED
IPC分类号： H02N01/00
CPC分类号： H02N1/004
摘要： An electrostatic actuator includes a sensing means for observing a position and the distribution state of electric charges without losing any special property of the actuator, and further, can be driven effectively at a high-speed. The actuator includes a first member (5) having a plurality of bank-like driving electrodes (2); a second member (6) in contact with the first member; a controlling means (9) for moving at least one of the first and second member by switching over the applied voltages of the driving electrodes to each other; sensing electrodes (4) positioned at predetermined phase intervals and isolated from the driving electrodes (2) of the first member (5); and a means for sensing the position of the second member and the distribution state of the electric charges induced thereon by sensing the electric signals induced on the sensing electrodes (4) through the distribution of the electric charge of the second member (6).

26. 发明申请

WO1992021084A1 POINTING DEVICE AND CONTROLLING METHOD THEREFOR 审中-公开
标题翻译：指示装置及其控制方法
公开(公告)号：WO1992021084A1
公开(公告)日：1992-11-26
申请号：PCT/JP1992000629
申请日：1992-05-15
申请人： FUJITSU LIMITED , ARITA, Takashi , SAKAGUCHI, Akihiko , OKAHASHI, Masanori , TANAKA, Toshiaki
发明人： FUJITSU LIMITED
IPC分类号： G06F03/033
CPC分类号： G06F3/038 , G05G1/06 , G05G9/047 , G05G9/04788 , G05G2009/04755 , G06F1/1616 , G06F1/1632 , G06F1/169 , G06F3/0338 , G06F2203/0331
摘要： A pointing device which moves a cursor on the display of a computer to an arbitrary position by a slider (1), having a means for changing over a position control, for controlling the position of the cursor to a speed control for controlling the speed of the movement of the cursor, according to the range of the movement of the slider.

27. 发明申请

WO1992017000A1 CIRCUIT FOR CONVERTING LEVEL 审中-公开
标题翻译：转换电路
公开(公告)号：WO1992017000A1
公开(公告)日：1992-10-01
申请号：PCT/JP1992000325
申请日：1992-03-18
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , SEKI, Teruo , UKAI, Hiroaki
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H03K19/0175
CPC分类号： H03K19/017554 , H03K19/00369 , H03K19/017527
摘要： A circuit for converting a first logical level into a second one. Even when the voltage of a power supply is increased, the low level of the output voltage of a switching circuit (25) is suppressed from increasing, and accordingly an output buffer (28) is always made operable, because voltage limiting elements (26, 27) suppress the output level shift voltages of level-shifting devices (21, 22) connected to the output ends of input transistors (Q1, Q2) to predetermined values.

28. 发明申请

WO1992012535A1 PROCESS FOR FORMING SILICON OXIDE FILM 审中-公开
标题翻译：形成硅氧烷膜的工艺
公开(公告)号：WO1992012535A1
公开(公告)日：1992-07-23
申请号：PCT/JP1991001739
申请日：1991-12-19
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , TSUKUNE, Atsuhiro , FURUMURA, Yuji , HATANAKA, Masanobu
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： H01L21/312
CPC分类号： H01L21/02164 , H01L21/02126 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/3121 , H01L21/3122 , H01L21/316 , H01L21/76819
摘要： A process for forming a silicon oxide film comprising the step of depositing a thin film of a silanol, a polymer thereof or a siloxane polymer, each containing an organic group, on a substrate by exciting a gas containing an organosilane or organosiloxane gas and a gas containing H and OH on a substrate in a reaction chamber to cause a reaction in a gas phase or on the substrate and the step of removing the organic group from the thin film by plasma treatment. Preferably the thin film is formed by repeating the depositing step and the removing step in the same chamber and is heat treated at a temperature of 450 °C or below. This process provides a good insulation film having a flatness comparable to that of an SOG film.

29. 发明申请

WO1992009084A1 SEMICONDUCTOR MEMORY HAVING HIGH-SPEED ADDRESS DECODER 审中-公开
标题翻译：具有高速地址解码器的半导体存储器
公开(公告)号：WO1992009084A1
公开(公告)日：1992-05-29
申请号：PCT/JP1991001563
申请日：1991-11-15
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED , KAWAMOTO, Satoru
发明人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
IPC分类号： G11C11/406
CPC分类号： G11C8/00 , G11C11/406 , G11C11/408
摘要： A semiconductor memory comprising a memory cell array (1), a first address bus (2) for transferring external address signals, a second address bus (3) for transferring internal address signals, an address decoder (4), and a controller (5); wherein the address decoder (4) includes a decoding section (4A) for decoding the address signal inputted to the address decoder (4) to select the predetermined word line of the memory cell array (1) and a changing section (4B) for changing the address signal to be inputted to the decoding section (4A) to the external or internal address signal by selecting either of the first and second address buses (2 and 3). Thus, it is possible to decrease the transfer time by transferring the external and internal address signals to the address decoder (4) through the first and second address buses (2 and 3) in accordance with an address activation signal before operation mode is decided and accelerate the access time of the memory cell by decreasing the decoding time.

30. 发明申请

WO1992006923A1 METHOD OF MAKING SUPERCONDUCTIVE FILM 审中-公开
标题翻译：制造超薄膜的方法
公开(公告)号：WO1992006923A1
公开(公告)日：1992-04-30
申请号：PCT/JP1991001423
申请日：1991-10-17
申请人： FUJITSU LIMITED , TANAKA, Atsushi , KAMEHARA, Nobuo , NIWA, Koichi
发明人： FUJITSU LIMITED
IPC分类号： C01G29/00
CPC分类号： C23C14/5806 , C23C14/087 , C23C14/58 , C23C14/5853 , H01L39/2451 , Y10S505/728 , Y10S505/73 , Y10S505/731 , Y10S505/742
摘要： A method of making a Bi-family perovskite type superconductive film comprising such processes that: a film of Pb-containing Bi-family material containing Bi, Pb, Sr, Ca, and Cu in the molar ratio of (1.9 to 2.1):(1.2 to 2.3, preferably, 1.5 to 1.8):2:(1.9 to 2.2):(3 to 3.5) is formed on a substrate, and then baked for 20 to 120 min in an oxygen-containing atmosphere with a temperature rise of 3 to 10 °C, preferably 3 to 5 °C until a final temperature of 850 to 860 °C, preferably 852 to 855 °C, is attained.

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