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11. 发明申请

WO2007008173A1 SEMICONDUCTOR STRUCTURE FOR TRANSISTORS WITH ENHANCED SUBTHRESHOLD SWING AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：具有增强子午线振荡的晶体管的半导体结构及其制造方法
公开(公告)号：WO2007008173A1
公开(公告)日：2007-01-18
申请号：PCT/SG2006/000093
申请日：2006-04-11
申请人： NATIONAL UNIVERSITY OF SINGAPORE , TOH, Eng Huat , YEO, Yee Chia , GANESH, S. Samudra
发明人： TOH, Eng Huat , YEO, Yee Chia , GANESH, S. Samudra
IPC分类号： H01L29/06 , H01L21/8232 , H01L27/085
CPC分类号： H01L27/092 , H01L21/823814 , H01L27/1203 , H01L29/517 , H01L29/518 , H01L29/66628 , H01L29/66636 , H01L29/66659
摘要： The semiconductor device (100) comprises a substrate structure (104); a gate stack (102) formed on said substrate structure (104); a drain region (122) of a first dopant type formed in the substrate structure (104) adjacent said gate stack (102); a source structure (126) formed on said substrate structure (104) adjacent said gate stack (102), the source structure (126) comprising a source region (132) of a second dopant type and a first region of a dopant concentration below 10 18 cm -3 disposed between the source region (132) and the substrate structure (104). The impact ionization metal-oxide semiconductor (IMOS) device has application as an inverter or integration into integrated circuit chips.
摘要翻译：半导体器件（100）包括衬底结构（104）; 形成在所述衬底结构（104）上的栅叠层（102）; 形成在所述栅叠层（102）附近的所述衬底结构（104）中的第一掺杂剂类型的漏区（122）; 形成在所述衬底结构（104）上邻近所述栅叠层（102）的源结构（126），所述源结构（126）包括第二掺杂剂类型的源区（132）和掺杂剂浓度低于10的第一区设置在源极区域（132）和衬底结构（104）之间的 30cm -3。冲击电离金属氧化物半导体（IMOS）器件作为逆变器应用或集成到集成电路芯片中。

12. 发明申请

WO02041401A1 SEMICONDUCTOR DEVICE AND PORTABLE ELECTRONIC APPARATUS 审中-公开
标题翻译：半导体器件和便携式电子设备
公开(公告)号：WO02041401A1
公开(公告)日：2002-05-23
申请号：PCT/JP2001/009887
申请日：2001-11-13
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , G06F17/60 , H01L27/085
CPC分类号： H01L21/76229 , H01L21/823892 , H01L27/092 , H01L27/0921
摘要： A semiconductor device of low power consumption and high reliability with a DTMOS and a substrate bias variable transistor and a portable electronic apparatus comprising this semiconductor device. This device has three layer well regions (12, 14, 16; 13, 15, 16) on a semiconductor substrate (11) and is provided with DTMOSs (29, 30), and substrate bias variable transistors (27, 28) in shallow well regions (16, 17). A boundary which constitutes a PNP, an NPN, or an NPNP structure is provided with wide element isolating regions (181, 182, 183), but a narrow element isolating region (18) when both the well regions have the same conductivity type. Thus, a plurality of well regions of respective conductivity types provided with substrate bias variable transistors (27, 28) of the respective conductivity types are made electrically independent to reduce power consumption and to suppress latchup phenomenon.
摘要翻译：一种具有DTMOS和衬底偏置可变晶体管的低功耗和高可靠性的半导体器件，以及包括该半导体器件的便携式电子设备。该器件在半导体衬底（11）上具有三层阱区（12,14,16; 13,15,16），并且具有DTMOS（29,30）和浅层衬底偏置可变晶体管（27,28）井区（16,17）。构成PNP，NPN或NPNP结构的边界设置有宽元件隔离区域（181,182,183），但是当两个阱区域具有相同的导电类型时，都具有窄元件隔离区域（18）。因此，设置有各种导电类型的衬底偏置可变晶体管（27,28）的各种导电类型的多个阱区域被电独立以降低功耗并且抑制闭锁现象。

13. 发明申请

WO2022082452A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF 审中-公开
公开(公告)号：WO2022082452A1
公开(公告)日：2022-04-28
申请号：PCT/CN2020/122263
申请日：2020-10-20
申请人： INNOSCIENCE (SUZHOU) TECHNOLOGY CO., LTD.
发明人： DU, Weixing , YOU, Jheng-Sheng
IPC分类号： H01L27/085 , H01L21/8232
摘要： A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

14. 发明申请

WO2021257180A1 INTEGRATED TRANSISTORS WITH SHARED ELECTRODE 审中-公开
公开(公告)号：WO2021257180A1
公开(公告)日：2021-12-23
申请号：PCT/US2021/028740
申请日：2021-04-23
申请人： MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
发明人： SOM, Shamit , ATHERTON, John Stephen , STRUBLE, Wayne Mack , BARRETT, Jason Matthew , YAMUJALA, Nishant R.
IPC分类号： H01L21/8234 , H01L23/48 , H01L23/528 , H01L27/02 , H01L27/085 , H01L29/417 , H03F1/02 , H01L21/8252 , H01L27/06 , H01L29/20 , H01L21/823475 , H01L23/481 , H01L23/4824 , H01L23/5226 , H01L23/5286 , H01L27/0207 , H01L27/0605 , H01L27/0617 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/778 , H03F1/0288 , H03F2200/451 , H03F3/195
摘要： Integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature (220) to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

15. 发明申请

WO2021255039A1 DISPOSITIF MICRO-ÉLECTRONIQUE À SUBSTRAT ISOLÉ, ET PROCÉDÉ DE FABRICATION ASSOCIÉ 审中-公开
公开(公告)号：WO2021255039A1
公开(公告)日：2021-12-23
申请号：PCT/EP2021/066138
申请日：2021-06-15
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： BUCKLEY, Julien , ESCOFFIER, René , GILLOT, Charlotte
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/085 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/778 , H01L29/66 , H01L29/207 , H01L29/861 , H01L27/0605 , H01L29/1066 , H01L29/1075 , H01L29/41766 , H01L29/66462 , H01L29/7786
摘要： L'invention concerne un dispositif (1) micro-électronique comprenant un premier (10) et un deuxième (20)composants électroniques, et un substrat (2), formé d'un premier matériau semi-conducteur, servant de support auxdits composants. Les premier et deuxième composants comprennent chacun une couche active (14, 24)formée au moins en partie d'un deuxième matériau semi-conducteur différent du premier matériau semi-conducteur. Le dispositif comprend en outre, pour chacun desdits composants, un empilement (100, 200) de maintien de tension électrique, qui est situé entre le substrat et la couche active du composant électronique considéré et qui comprend deux couches formant un jonction P-N, formée à partir du même matériau semi-conducteur que le substrat et qui isole la couche active en question d'avec le substrat. Les ensembles comprenant respectivement le premier et le deuxième composant et son empilement respectif de maintien de tension électrique sont séparés l'un de l'autre par une barrière (4) en matériau électriquement isolant (5). L'invention concerne aussi un procédé de fabrication associé.

16. 发明申请

WO2021050194A1 GAUSSIAN SYNAPSES FOR PROBABILISTIC NEURAL NETWORKS 审中-公开
公开(公告)号：WO2021050194A1
公开(公告)日：2021-03-18
申请号：PCT/US2020/045969
申请日：2020-08-12
申请人： THE PENN STATE RESEARCH FOUNDATION
发明人： DAS, Saptarshi , SEBASTIAN, Amritanand
IPC分类号： H01L27/085 , H01L29/775
摘要： Embodiments relate to a Gaussian synapse device configured so that its transfer characteristics resemble a Gaussian distribution. Embodiments of the Gaussian synapse device include an n-type field-effect transistor (FET) and p-type FET with a common contact so that the two FETs are connected in series. Some embodiments include a global back-gate contact and separate top-gate contact to obtain dual-gated FETs. Some embodiments include two different 2D materials used in the channel to generate the two FETs, while some embodiments use a single ambipolar transport material. In some embodiments, the dual-gated structure is used to dynamically control the amplitude, mean and standard deviation of the Gaussian synapse. In some embodiments, the Gaussian synapse device can be used as a probabilistic computational device (e.g., used to form a probabilistic neural network).

17. 发明申请

WO2018041192A1 集成有结型场效应晶体管的器件及其制造方法审中-公开
公开(公告)号：WO2018041192A1
公开(公告)日：2018-03-08
申请号：PCT/CN2017/099841
申请日：2017-08-31
申请人：无锡华润上华科技有限公司
发明人：顾炎 , 程诗康 , 张森
IPC分类号： H01L29/78 , H01L27/085 , H01L21/8232
摘要：一种集成有结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极（201），具有第一导电类型，所述漏极（201）的一部分位于所述JFET区、另一部分位于所述功率器件区；及第一导电类型区，设于所述漏极（201）的正面，所述第一导电类型区的一部分位于所述JFET区、另一部分位于所述功率器件区；所述JFET区包括：第一阱（205），具有第二导电类型且形成于所述第一导电类型区内；第二阱（207），具有第二导电类型且形成于所述第一导电类型区内，离子浓度大于所述第一阱（205）的离子浓度；所述第一导电类型和第二导电类型相反；JFET源极（212），具有第一导电类型；金属电极，形成于所述JFET源极（212）上且与所述JFET源极（212）接触；及第二导电类型埋层（203），形成于所述JFET源极（212）和第二阱（207）下方。

18. 发明申请

WO2017123305A2 REDUCED OVERHEAD GATE LEVEL LOGIC ENCRYPTION 审中-公开
标题翻译：降低开门水平逻辑加密
公开(公告)号：WO2017123305A2
公开(公告)日：2017-07-20
申请号：PCT/US2016/058393
申请日：2016-10-24
申请人： DREXEL UNIVERSITY , JURETUS, Kyle , SAVIDIS, Ioannis
发明人： JURETUS, Kyle , SAVIDIS, Ioannis
IPC分类号： H04L9/12 , H01L27/085
CPC分类号： G09C1/00 , H04L2209/046 , H04L2209/12 , H04L2209/16
摘要： There are several approaches to encrypting circuits: combination logic encryption, encrypted gate topologies, transmission gate topologies, and key expansion of gate topologies. Each of these may encrypt a circuit with certain advantages in delay and power consumption.
摘要翻译：有几种加密电路的方法：组合逻辑加密，加密栅极拓扑，传输栅极拓扑和栅极拓扑的关键扩展。它们中的每一个都可以加密具有延迟和功耗优点的电路。

19. 发明申请

WO2016113468A1 A SEMICONDUCTOR LOGIC ELEMENT AND A LOGIC CIRCUITRY 审中-公开
标题翻译：半导体逻辑元件和逻辑电路
公开(公告)号：WO2016113468A1
公开(公告)日：2016-07-21
申请号：PCT/FI2016/050014
申请日：2016-01-13
申请人： AUROLA, Artto Mikael
发明人： AUROLA, Artto Mikael
IPC分类号： H03K19/094 , H01L27/085 , H03K19/003 , H03K19/20 , H03K19/0952
CPC分类号： H03K19/20 , H01L27/0207 , H01L27/0629 , H01L27/092 , H01L27/098 , H01L27/1203 , H01L29/0692 , H01L29/7838 , H01L29/808 , H01L29/8083 , H03K19/0013 , H03K19/00315 , H03K19/094 , H03K19/0952
摘要： The invention relates to a semiconductor logic element comprising a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. The invention relates also to different kinds of logic circuitries comprising the described logic element.
摘要翻译：本发明涉及包括第一导电类型的场效应晶体管和第二导电类型的场效应晶体管的半导体逻辑元件。第一FET的栅极是半导体逻辑元件的输入，第二FET的漏极被称为半导体逻辑元件的输出，第二FET的源极是半导体逻辑元件的源极。通过将适用的电位施加到场效应晶体管的端子，可以影响逻辑元件的输出状态。本发明还涉及包括所描述的逻辑元件的不同种类的逻辑电路。

20. 发明申请

WO2015171873A1 TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS 审中-公开
标题翻译：拥有岛屿地区的晶体管结构
公开(公告)号：WO2015171873A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/029656
申请日：2015-05-07
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： LU, Bin , PALACIOS, Tomas , XIA, Ling , AZIZE, Mohamed
IPC分类号： H01L27/088 , H01L27/085 , H01L27/08
CPC分类号： H01L21/02565 , H01L21/02527 , H01L21/02529 , H01L21/02532 , H01L21/0254 , H01L21/283 , H01L29/0619 , H01L29/0623 , H01L29/0646 , H01L29/0649 , H01L29/1033 , H01L29/1037 , H01L29/1041 , H01L29/1054 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/22 , H01L29/4236 , H01L29/42368 , H01L29/66462 , H01L29/7786 , H01L29/78 , H01L29/861
摘要： A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.
摘要翻译：诸如晶体管的半导体器件包括源极区，漏极区，半导体区，至少一个岛区和至少一个栅极区。半导体区域位于源极区域和漏极区域之间。岛屿地区位于半导体区域。每个岛区域与选自包括电阻率，掺杂类型，掺杂浓度，应变和材料组成的组中的一个或多个特性中的半导体区域不同。栅极区域位于覆盖岛状区域的至少一部分的源极区域和漏极区域之间。

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