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1. 发明申请

WO2017027704A1 SEMICONDUCTOR STRUCTURE WITH A SPACER LAYER 审中-公开
标题翻译：具有间隔层的半导体结构
公开(公告)号：WO2017027704A1
公开(公告)日：2017-02-16
申请号：PCT/US2016/046546
申请日：2016-08-11
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： AZIZE, Mohamed , LU, Bin , XIA, Ling
IPC分类号： H01L29/66 , H01L27/14 , H01L29/15
CPC分类号： H01L29/7786 , H01L29/155 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/432 , H01L29/66462 , H01L29/872
摘要： A multi-layer semiconductor structure is disclosed for use in Ill-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material A1 ϰ IN γ Ga z N in which 0≤x≤1,0≤y≤1, and 0≤z≤1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
摘要翻译：公开了一种用于III族氮化物半导体器件的多层半导体结构，包括沟道层，具有比沟道层宽的带隙的带隙偏移层，具有比带隙偏移层窄的带隙的间隔层，以及包括至少两个子层的覆盖层。每个子层相对于紧下面和上面的子层可选择性地蚀刻，每个子层包括其中0≤x≤1,0≤y≤1且0≤z≤1的III-N材料A1κINγGazN，至少一个子层具有非零Ga含量，紧靠在间隔层上方的子层具有比间隔层更宽的带隙。还描述了制造这种半导体结构的方法，其中通过选择性地去除相邻的层或子层形成栅极和/或欧姆凹槽。提高了所得设备的性能，同时提供了设计灵活性来降低生产成本和电路占用空间。

2. 发明申请

WO2017176612A1 SEMICONDUCTOR STRUCTURE AND ETCH TECHNIQUE FOR MONOLITHIC INTEGRATION OF III-N TRANSISTORS 审中-公开
标题翻译： III-N晶体管单片集成的半导体结构和蚀刻技术
公开(公告)号：WO2017176612A1
公开(公告)日：2017-10-12
申请号：PCT/US2017/025685
申请日：2017-04-03
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： XIA, Ling , AZIZE, Mohamed , LU, Bin
IPC分类号： H01L29/66 , H01L27/088 , H01L21/336
摘要： Semiconductor structures are disclosed for monolithically integrating multiple III-N transistors with different threshold voltages on a common substrate. A semiconductor structure includes a cap layer comprising a plurality of selectively etchable sublayers, wherein each sublayer is selectively etchable with respect to the sublayer immediately below, wherein each sublayer comprises a III-N material A1 x In y Ga z N (0 ≤ x, y, z ≤ 1), and wherein at least one selectively etchable sublayer has a non-zero Ga content (0
摘要翻译：公开了用于将具有不同阈值电压的多个III-N晶体管单片集成在公共衬底上的半导体结构。半导体结构包括具有多个可选择性蚀刻的子层的盖层，其中每个子层相对于正下方的子层是可选择性蚀刻的，其中每个子层包含III-N材料AlNxInIn （0≤x，y，z≤1），并且其中至少一个选择性可蚀刻子层具有非零Ga含量（0

3. 发明申请

WO2015171705A1 NUCLEATION AND BUFFER LAYERS FOR GROUP III-NITRIDE BASED SEMICONDUCTOR DEVICES 审中-公开
标题翻译：基于III-NITRIDE的半导体器件的晶核和缓冲层
公开(公告)号：WO2015171705A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/029382
申请日：2015-05-06
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： AZIZE, Mohamed , XIA, Ling , LU, Bin , PALACIOS, Tomas
IPC分类号： H01L29/12 , H01L29/24 , H01L33/12 , H01L33/26
CPC分类号： H01L29/2003 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02631 , H01L23/291 , H01L23/3171 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/7787 , H01L33/007 , H01L33/12 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer includes a substrate and at least one nucleation layer overlying the substrate. The nucleation layer includes a Al x Si y C z N w O t composition with 0≤x≤1, 0≤y≤1, 0≤z≤1, 0≤w≤1, 0≤t≤1, and x x y>0 and with any additional impurities being less than 10% of the Al x Si y C z N w O t composition. The semiconductor wafer also includes a buffer layer structure overlying the nucleation layer. The buffer layer structure including at least one layer having a group III nitride composition.
摘要翻译：半导体晶片包括衬底和覆盖衬底的至少一个成核层。成核层包括具有0≤x≤1,0≤y≤1,0≤z≤1,0≤w≤1,0≤t≤1和xxy> 0的任何附加杂质的Al x S y C z N w O t组合物 10％的AlxSiyCzNwOt组成。半导体晶片还包括覆盖成核层的缓冲层结构。该缓冲层结构包括至少一层具有III族氮化物组合物的层。

4. 发明申请

WO2015077647A2 ELECTRIC FIELD MANAGEMENT FOR A GROUP III-NITRIDE SEMICONDUCTOR 审中-公开
标题翻译：用于III类氮化物半导体的电场管理
公开(公告)号：WO2015077647A2
公开(公告)日：2015-05-28
申请号：PCT/US2014/066951
申请日：2014-11-21
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： LU, Bin , PALACIOS, Tomas , XIA, Ling , AZIZE, Mohamed
IPC分类号： H01L29/778 , H01L29/20 , H01L29/40
CPC分类号： H01L29/7787 , H01L29/0607 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/402 , H01L29/405 , H01L29/41725
摘要： A semiconductor device includes a substrate, a first active layer, a second active layer, at least first and second electrodes, an E-field management layer, and at least one injection electrode. The first active layer is disposed over the substrate. The second active layer is disposed on the first active layer such that a laterally extending conductive channel arises which extends in a lateral direction. The laterally extending conductive channel is located between the first active layer and the second active layer. The first and second electrodes are electrically connected to the first active layer. The E-field management layer, which reduces the electric-field gradients arising in the first and second active layers, is disposed over the second active layer. The injection electrode is electrically connected to the E-field management layer.
摘要翻译：半导体器件包括衬底，第一有源层，第二有源层，至少第一和第二电极，E场管理层和至少一个注入电极。第一有源层设置在衬底上。第二有源层设置在第一有源层上，使得出现沿横向方向延伸的横向延伸的导电通道。横向延伸的导电通道位于第一有源层和第二有源层之间。第一和第二电极电连接到第一有源层。减少在第一和第二有源层中出现的电场梯度的电场管理层设置在第二有源层上。注入电极与E场管理层电连接。

5. 发明申请

WO2017015225A1 FIELD-PLATE STRUCTURES FOR SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件的现场板结构
公开(公告)号：WO2017015225A1
公开(公告)日：2017-01-26
申请号：PCT/US2016/042831
申请日：2016-07-18
申请人： CAMBRIDGE ELECTRONICS, INC. , XIA, Ling , AZIZE, Mohamed , LU, Bin
发明人： XIA, Ling , AZIZE, Mohamed , LU, Bin
IPC分类号： H01L29/66 , H01L29/02 , H01L31/02
CPC分类号： H01L29/404 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L29/2003 , H01L29/402 , H01L29/405 , H01L29/407 , H01L29/41766 , H01L29/42316 , H01L29/4236 , H01L29/452 , H01L29/454 , H01L29/475 , H01L29/66181 , H01L29/7786 , H01L29/861 , H01L29/94
摘要： Field-plate structures are disclosed for electrical field management in semiconductor devices. A field-plate semiconductor structure includes a semiconductor substrate, a source ohmic contact, a drain ohmic contact, and a gate contact disposed over a gate region between the source ohmic contact and the drain ohmic contact, and a source field plate connected to the source ohmic contact. A field-plate dielectric is disposed over the semiconductor substrate. An encapsulating dielectric is disposed over the gate contact, wherein the encapsulating dielectric covers a top surface of the gate contact. The source field plate is disposed over the field-plate dielectric in a field plate region, from which the encapsulating dielectric is absent.
摘要翻译：公开了用于半导体器件中的电场管理的场板结构。场板半导体结构包括半导体衬底，源欧姆接触，漏极欧姆接触和设置在源极欧姆接触和漏极欧姆接触之间的栅极区域上的栅极接触，以及连接到源极的源极场欧姆接触。场致电介质设置在半导体衬底之上。封装电介质设置在栅极触点上方，其中封装电介质覆盖栅极触点的顶表面。源场板在场板区域中设置在场板电介质上，不存在封装电介质。

6. 发明申请

WO2015171873A1 TRANSISTOR STRUCTURE HAVING BURIED ISLAND REGIONS 审中-公开
标题翻译：拥有岛屿地区的晶体管结构
公开(公告)号：WO2015171873A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/029656
申请日：2015-05-07
申请人： CAMBRIDGE ELECTRONICS, INC.
发明人： LU, Bin , PALACIOS, Tomas , XIA, Ling , AZIZE, Mohamed
IPC分类号： H01L27/088 , H01L27/085 , H01L27/08
CPC分类号： H01L21/02565 , H01L21/02527 , H01L21/02529 , H01L21/02532 , H01L21/0254 , H01L21/283 , H01L29/0619 , H01L29/0623 , H01L29/0646 , H01L29/0649 , H01L29/1033 , H01L29/1037 , H01L29/1041 , H01L29/1054 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/22 , H01L29/4236 , H01L29/42368 , H01L29/66462 , H01L29/7786 , H01L29/78 , H01L29/861
摘要： A semiconductor device such as a transistor includes a source region, a drain region, a semiconductor region, at least one island region and at least one gate region. The semiconductor region is located between the source region and the drain region. The island region is located in the semiconductor region. Each of the island regions differs from the semiconductor region in one or more characteristics selected from the group including resistivity, doping type, doping concentration, strain and material composition. The gate region is located between the source region and the drain region covering at least a portion of the island regions.
摘要翻译：诸如晶体管的半导体器件包括源极区，漏极区，半导体区，至少一个岛区和至少一个栅极区。半导体区域位于源极区域和漏极区域之间。岛屿地区位于半导体区域。每个岛区域与选自包括电阻率，掺杂类型，掺杂浓度，应变和材料组成的组中的一个或多个特性中的半导体区域不同。栅极区域位于覆盖岛状区域的至少一部分的源极区域和漏极区域之间。

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