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11. 发明申请

WO2006123105A2 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：WO2006123105A2
公开(公告)日：2006-11-23
申请号：PCT/GB2006001724
申请日：2006-05-11
申请人： CAMBRIDGE SEMICONDUCTOR LTD , UDREA FLORIN
发明人： UDREA FLORIN
IPC分类号： H01L29/739 , H01L21/331 , H01L29/08
CPC分类号： H01L29/7394 , H01L29/0839 , H01L29/7432 , H01L29/745 , H01L29/861 , H01L29/872
摘要： A bipolar high voltage/power semiconductor device (1) has a low voltage terminal and a high voltage terminal. The device (1) has a drift region (2) of a first conductivity type and having first and second ends. In one example, a region (5) of the second conductivity type is provided at the second end of the drift region (2) connected directly to the high voltage terminal. In another example, a buffer region (6) of the first conductivity type is provided at the second end of the drift region (2) and a region (5) of the second conductivity type is provided on the other side of the buffer region (6) and connected to the high voltage terminal. Plural electrically floating island regions (9) are provided within the drift region (2) at or towards the second end of the drift region (2), the plural electrically floating island regions (9) being of the first conductivity type and being more highly doped than the drift region (2) .
摘要翻译：双极高压/功率半导体器件（1）具有低电压端子和高压端子。装置（1）具有第一导电类型的漂移区（2），并具有第一和第二端。在一个示例中，第二导电类型的区域（5）设置在直接连接到高电压端子的漂移区域（2）的第二端。在另一示例中，在漂移区域（2）的第二端设置第一导电类型的缓冲区域（6），并且在缓冲区域的另一侧设置第二导电类型的区域（5） 6）并连接到高压端子。在漂移区域（2）内的或位于漂移区域（2）的第二端处的多个电浮岛区域（9）设置在漂移区域（2）内，多个电浮岛区域（9）是第一导电类型并且更高掺杂比漂移区（2）。

12. 发明申请

WO2012054686A2 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 审中-公开
标题翻译：带有改进的终端结构的高电压应用的沟槽式DMOS器件
公开(公告)号：WO2012054686A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057020
申请日：2011-10-20
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-Wei , UDREA, Florin , LIN, Yih-Yin
发明人： HSU, Chih-Wei , UDREA, Florin , LIN, Yih-Yin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/063 , H01L29/0661 , H01L29/407 , H01L29/66143 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.
摘要翻译：用于功率晶体管的终端结构包括具有有源区和终端区的半导体衬底。衬底具有第一类型的导电性。终止沟槽位于终止区域中并且从有源区域的边界延伸到半导体衬底的边缘的一定距离内。掺杂区域具有设置在终止沟槽下方的衬底中的第二类型的导电性。 MOS栅极形成在与边界相邻的侧壁上。掺杂区域从与边界间隔开的MOS栅极的一部分的下方朝向终端沟槽的远端侧壁延伸。端接结构氧化物层形成在终端沟槽上并且覆盖MOS栅极的一部分并且朝向衬底的边缘延伸。第一导电层形成在半导体衬底的背侧表面上。第二导电层形成在MOS栅极的暴露部分的有源区顶上，并且延伸以覆盖终止结构氧化物层的至少一部分。

13. 发明申请

WO2012054682A2 IMPROVED SCHOTTKY RECTIFIER 审中-公开
标题翻译：改进的肖特基整流器
公开(公告)号：WO2012054682A2
公开(公告)日：2012-04-26
申请号：PCT/US2011/057012
申请日：2011-10-20
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
发明人： HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
IPC分类号： H01L29/872 , H01L29/868 , H01L21/329
CPC分类号： H01L29/66143 , H01L21/22 , H01L21/265 , H01L29/0619 , H01L29/872 , H01L29/8725
摘要： A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
摘要翻译：半导体整流器包括具有第一类导电性的半导体衬底。形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。第一电极形成在金属层的上方，第二电极形成在基板的背面。

14. 发明申请

WO2011115775A1 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS 审中-公开
标题翻译： TRENCH DMOS器件具有改进的高压应用终止结构
公开(公告)号：WO2011115775A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/027464
申请日：2011-03-08
申请人： VISHAY GENERAL SEMICONDUCTOR LLC , HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
发明人： HSU, Chih-wei , UDREA, Florin , LIN, Yih-yin
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L29/0615 , H01L29/0661 , H01L29/404 , H01L29/66143 , H01L29/7811 , H01L29/7813 , H01L29/872 , H01L29/8725
摘要： A termination structure is provided for a power transistor. The termination structure includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region toward an edge of the semiconductor substrate. A doped region having a second type of conductivity is disposed in the substrate below the termination trench. A MaS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion ofthe MaS gate spaced apart from the boundary toward the edge ofthe semiconductor substrate. A termination structure oxide layer is formed on the termination trench covering a portion of the MaS gate and extends toward the edge of the substrate.
摘要翻译：为功率晶体管提供端接结构。端接结构包括具有有源区和端接区的半导体衬底。衬底具有第一类导电性。终端沟槽位于终端区域中并且从有源区域的边界朝向半导体衬底的边缘延伸。具有第二类型的导电性的掺杂区域设置在终端沟槽下方的衬底中。 MaS门形成在与边界相邻的侧壁上。掺杂区域从距离边界的半导体衬底的边缘间隔开的MaS栅极的一部分的下方延伸。端接结构氧化物层形成在覆盖MaS栅极的一部分并且朝向衬底边缘延伸的端接沟槽上。

15. 发明申请

WO2011030152A1 LATERAL INSULATED GATE BIPOLAR TRANSISTORS (LIGBTs) 审中-公开
标题翻译：横向绝缘门双极晶体管（LIGBT）
公开(公告)号：WO2011030152A1
公开(公告)日：2011-03-17
申请号：PCT/GB2010/051505
申请日：2010-09-09
申请人： CAMBRIDGE SEMICONDUCTOR LIMITED , UDREA, Florin , TRAJKOVIC, Tanya , PATHIRANA, Vasantha , UDUGAMPOLA, Nishad
发明人： UDREA, Florin , TRAJKOVIC, Tanya , PATHIRANA, Vasantha , UDUGAMPOLA, Nishad
IPC分类号： H01L21/331 , H01L29/739
CPC分类号： H01L29/7394 , H01L29/66325 , H01L29/7393
摘要： This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv
摘要翻译：本发明一般涉及横向绝缘栅双极晶体管（LIGBT），例如在集成电路中，提高LIGBT的开关速度的方法，抑制体硅LIGBT中的寄生晶闸管闩锁的方法以及制造LIGBT的方法。特别地，抑制体硅LIGBT中的寄生晶闸管闩锁的方法包括为LIGBT的寄生晶闸管的垂直晶体管选择电流增益av，使得在LIGBT av <1的至少一个预定操作模式其中ap是具有由半导体表面和富含金属的环氧树脂芯片附着之间的肖特基接触形成的基极 - 发射极结的寄生双极晶体管的电流增益。

16. 发明申请

WO2007026177A1 GAS-SENSING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：气体传感半导体器件
公开(公告)号：WO2007026177A1
公开(公告)日：2007-03-08
申请号：PCT/GB2006/050199
申请日：2006-07-12
申请人： UNIVERSITY OF WARWICK , GARDNER, Julian William , UDREA, Florin , IWAKI, Takao , COVINGTON, James Anthony
发明人： GARDNER, Julian William , UDREA, Florin , IWAKI, Takao , COVINGTON, James Anthony
IPC分类号： G01N27/12 , G01N27/414 , G01N33/00
CPC分类号： G01N33/0047 , G01N27/14 , G01N33/0031
摘要： Gas-Sensing Semiconductor Devices A gas-sensing semiconductor device 1' is fabricated on a silicon substrate 2' having a thin silicon dioxide insulating layer 3' in which a resistive heater 6 made of doped single crystal silicon formed simultaneously with source and drain regions of CMOS circuitry is embedded. The device 1' includes a sensing area provided with a gas-sensitive layer 9' separated from the heater 6' by an insulating layer 4'. As one of the final fabrication steps, the substrate 2' is back-etched so as to form a thin membrane in the sensing area. The heater 6' has a generally circular-shaped structure surrounding a heat spreading plate 16', and consists of two sets 20', 21' of meandering resistors having arcuate portions nested within one another and interconnected in labyrinthine form. The fabrication of the heater at the same time as the source and drain regions of CMOS circuitry is particularly advantageous in that the gas-sensing semiconductor device is produced without requiring any fabrication steps in addition to those already employed in the IC processing apart from a post-CMOS back etch and deposition of the gas-sensitive layer. The circular design is advantageous in that it is the best solution to minimise the size of the membrane at fixed power loss and heated area.
摘要翻译：气体感测半导体器件气体感测半导体器件1'制造在具有薄二氧化硅绝缘层3'的硅衬底2'上，其中由掺杂单晶硅制成的电阻加热器6与源极和漏极区域同时形成嵌入CMOS电路。装置1'包括具有通过绝缘层4'与加热器6'分离的气敏层9'的感测区域。作为最终制造步骤之一，衬底2'被反蚀刻以在感测区域中形成薄膜。加热器6'具有围绕散热板16'的大致圆形结构，并且由具有彼此嵌套并且以迷宫形式互连的弓形部分的曲折电阻器的两组20'，21'组成。与CMOS电路的源极和漏极区域同时地制造加热器是特别有利的，因为除了在后处理中已经用于IC处理中的那些之外，制造气体感测半导体器件不需要任何制造步骤 -CMOS背蚀刻和气敏层的沉积。圆形设计是有利的，因为它是在固定功率损耗和加热面积下最小化膜尺寸的最佳解决方案。

17. 发明申请

WO2006027669A1 SWITCHING DEVICE 审中-公开
标题翻译：切换设备
公开(公告)号：WO2006027669A1
公开(公告)日：2006-03-16
申请号：PCT/IB2005/002654
申请日：2005-09-08
申请人： ELEMENT SIX LIMITED , KEMP, Mark , AMARATUNGA, Gehan, Anil, Joseph , BREZEANU, Mihai , RASHID, Jeremy, Suhail , RUPESINGHE, Nalin, Lalith , TAJANI, Antonella , TWITCHEN, Daniel, James , UDREA, Florin , WORT, Christopher, John, Howard
发明人： AMARATUNGA, Gehan, Anil, Joseph , BREZEANU, Mihai , RASHID, Jeremy, Suhail , RUPESINGHE, Nalin, Lalith , TAJANI, Antonella , TWITCHEN, Daniel, James , UDREA, Florin , WORT, Christopher, John, Howard
IPC分类号： H01L31/10
CPC分类号： H01L31/108 , H01L31/028 , H01L31/0288 , H01L31/118 , Y02E10/547
摘要： A high voltage diamond based switching device capable of sustaining high currents in the on state with a relatively low impedance and a relatively low optical switching flux. It is also capable of being switched off in the presence of the high voltage being switched. The device consists of a diamond body having a Schottky barrier contact, held in reverse bias by the applied voltage to be switched, to an essentially intrinsic diamond layer or portion in the diamond body, and a second metal contact. It also includes an optical source or other illuminating or irradiating means such that when the depletion region formed by the Schottky contact to the intrinsic diamond layer is exposed to its radiation charge carriers are generated. Gain in the total number of charge carriers then occurs as a result of these charge carriers accelerating under the field within the intrinsic diamond layer and generating further carriers in the manner of assisted avalanche breakdown.
摘要翻译：一种高电压金刚石开关器件，其能够以相对较低的阻抗和相对低的光学开关通量在导通状态下维持高电流。它还能够在存在正在切换的高电压的情况下关闭。该装置由具有肖特基势垒接触的金刚石体组成，该反射体通过施加的被切换的电压以相反的偏压保持在金刚石本体中基本上为本征的金刚石层或部分，以及第二金属接触。它还包括光源或其他照明或照射装置，使得当通过与本征金刚石层的肖特基接触形成的耗尽区域暴露于其辐射电荷载体时产生。然后，由于这些电荷载流子在本征金刚石层内的场下加速并且以辅助的雪崩击穿的方式产生其它载体，所以电荷载体总数的增益然后发生。

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