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101. 发明申请

WO2012119003A1 DISTRIBUTED BUILDING BLOCKS OF R-C CLAMPING CIRCUITRY IN SEMICONDUCTOR DIE CORE AREA 审中-公开
标题翻译：半导体芯片领域R-C钳位电路的分布式建筑块
公开(公告)号：WO2012119003A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/027337
申请日：2012-03-01
申请人： QUALCOMM INCORPORATED , JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
发明人： JALILIZEINALI, Reza , SIANSURI, Evan , DUNDIGAL, Sreeker, R. , WORLEY, Eugene R.
IPC分类号： H01L27/02
CPC分类号： H01L27/0285 , H01L27/0296 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die includes resistor-capacitor (RC) clamping circuitry for electrostatic discharge (ESD) protection of the semiconductor die. The RC clamping circuitry includes building blocks distributed in the pad ring and in the core area of the semiconductor die. The building blocks include at least one capacitor block in the core area. The RC clamping circuitry also includes chip level conductive layer connections between each of the distributed building blocks.
摘要翻译：半导体管芯包括用于半导体管芯的静电放电（ESD）保护的电阻 - 电容（RC）钳位电路。 RC钳位电路包括分布在焊盘环和半导体管芯的芯区域中的构建块。构建块包括核心区域中的至少一个电容器块。 RC钳位电路还包括每个分布式构建块之间的芯片级导电层连接。

102. 发明申请

WO2012112619A1 METHODS OF INTEGRATED SHIELDING INTO MTJ DEVICE FOR MRAM 审中-公开
标题翻译：用于MRAM的MTJ器件的集成屏蔽方法
公开(公告)号：WO2012112619A1
公开(公告)日：2012-08-23
申请号：PCT/US2012/025133
申请日：2012-02-14
申请人： QUALCOMM Incorporated , CHEN, Wei-Chuan , LI, Xia , KANG, Seung H.
发明人： CHEN, Wei-Chuan , LI, Xia , KANG, Seung H.
IPC分类号： G11C11/16 , H01L27/22 , H01L43/08
CPC分类号： G11C11/16 , G11C11/161 , H01L23/552 , H01L27/11502 , H01L27/11507 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus for shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.
摘要翻译：提供了用于屏蔽非易失性存储器的方法和装置，例如屏蔽磁性隧道结（MTJ）装置与磁通量。在一个示例中，屏蔽层邻近MTJ器件的电极形成，使得屏蔽层基本上围绕电极的表面，并且金属线耦合到屏蔽层。金属线可以通过通孔耦合到屏蔽层。

103. 发明申请

WO2012103477A1 HIGH VOLTAGE TOLERANT RECEIVER 审中-公开
标题翻译：高耐压接收器
公开(公告)号：WO2012103477A1
公开(公告)日：2012-08-02
申请号：PCT/US2012/022968
申请日：2012-01-27
申请人： QUALCOMM Incorporated , SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
发明人： SRIVASTAVA, Ankit , HUANG, Xuhao , QUAN, Xiaohong
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.
摘要翻译：高耐压单端接收器电路包括分压器，其可操作地将大于分压器的阈值电压的半个单端输入信号分频。通路门电路用于接收低于分压器的阈值电压的单端信号。来自分压器的输出耦合到修改的施密特触发电路的第一输入端，以控制施密特触发电路的高阈值电平。来自通路电路的输出耦合到修改的施密特触发电路的第二输入，以控制施密特触发电路的低阈值电平。

104. 发明申请

WO2012100255A1 READ SENSING CIRCUIT AND METHOD WITH EQUALIZATION TIMING 审中-公开
标题翻译：阅读感应电路和均衡时序方法
公开(公告)号：WO2012100255A1
公开(公告)日：2012-07-26
申请号：PCT/US2012/022239
申请日：2012-01-23
申请人： QUALCOMM INCORPORATED , KIM, Jung Pill , KIM, Tae Hyun
发明人： KIM, Jung Pill , KIM, Tae Hyun
IPC分类号： G11C11/16
CPC分类号： G11C7/08 , G11C11/1673
摘要： A Magnetic Random Access Memory (MRAM) includes read sensing circuitry having an equalizer device configured between a bit cell output node and a reference node of the bit cell. The equalizer is turned on to couple the output node to the reference node during an initial portion of a read operation and to decouple the output node from the reference node after an equalization delay period. A sense amplifier is enabled to provide a data output from the bit cell only after the delay period and decoupling of the output node from the reference node to provide balanced sensing speed of data represented by parallel and antiparallel state magnetic tunnel junctions (MTJs).
摘要翻译：磁性随机存取存储器（MRAM）包括具有配置在比特单元输出节点和比特单元的参考节点之间的均衡器装置的读取感测电路。在读操作的初始部分期间，均衡器被导通以将输出节点耦合到参考节点，并且在均衡延迟周期之后将输出节点与参考节点去耦。读出放大器能够仅在延迟周期之后从位单元提供数据输出，并且将输出节点与参考节点解耦，以提供由并行和反并联状态磁隧道结（MTJ）表示的数据的平衡感测速度。

105. 发明申请

WO2012097359A1 METHOD OF HALF-BIT PRE-EMPHASIS FOR MULTI-LEVEL SIGNAL 审中-公开
标题翻译：用于多级信号的半双工预处理方法
公开(公告)号：WO2012097359A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/021437
申请日：2012-01-16
申请人： QUALCOMM INCORPORATED , DANG, Harry H. , DANG, Vannam
发明人： DANG, Harry H. , DANG, Vannam
IPC分类号： H04L25/03
CPC分类号： H04L25/03834
摘要： Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal.
摘要翻译：提供了改善传输通道效率的方法和装置。在一个示例中，接收数字信号。预先强调数字信号中的位的前导部分。接收到的数字信号用预加重信号进行调制，以预先强调数字信号中位的前导部分。预加重信号基本上在时钟为高并且所接收的数字信号转变时提供预加重。当接收的数字信号为低或接收的数字信号不变时，预加重信号不提供预加重。然后通过传输信道传输预先强调的数字信号。在一个例子中，接收到的数字信号是脉冲幅度调制多电平信号。

106. 发明申请

WO2012097103A1 FULL DIGITAL BANG BANG FREQUENCY DETECTOR WITH NO DATA PATTERN DEPENDENCY 审中-公开
标题翻译：全数字BANG BANG频率检测器，无数据模式依赖
公开(公告)号：WO2012097103A1
公开(公告)日：2012-07-19
申请号：PCT/US2012/020995
申请日：2012-01-11
申请人： QUALCOMM Incorporated , KONG, Xiaohua , DANG, Nam V. , SOWLATI, Tirdad , AGGARWAL, Ashutosh
发明人： KONG, Xiaohua , DANG, Nam V. , SOWLATI, Tirdad , AGGARWAL, Ashutosh
IPC分类号： H04L7/033 , H03L7/087 , H03L7/089
CPC分类号： H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/0995
摘要： A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.
摘要翻译：提供了一种没有数据模式依赖性的爆轰频率检测器。在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。频率差可用于调整采样时钟的频率。锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。

107. 发明申请

WO2012078818A1 METHOD AND APPARATUS FOR FREQUENCY SYNTHESIZING 审中-公开
标题翻译：用于频率合成的方法和装置
公开(公告)号：WO2012078818A1
公开(公告)日：2012-06-14
申请号：PCT/US2011/063843
申请日：2011-12-07
申请人： QUALCOMM INCORPORATED , BO, Sun , GENG, Jifeng
发明人： BO, Sun , GENG, Jifeng
IPC分类号： H03K5/135 , H03K5/156 , H03L7/08
CPC分类号： H03K5/135 , H03K5/1565 , H03L7/0816 , H03L7/16
摘要： Systems and methods for frequency synthesis are disclosed. Exemplary embodiments of the digital frequency synthesizer (105) can produce a fixed frequency and/or a modulated signal (130). An exemplary digital frequency synthesizer includes series - coupled delay cells (210), a linear feedback shift register (225), and an accumulator (275). The series - coupled delay cells (210) generate, from an input clock signal (125), multiple clock edges (205) corresponding to fractional clock periods. A linear feedback shift register (225) selects clock edges to pass to a combinational logic circuit (255), based on a sign/enable control signal (230) received from an accumulator (275) and a clock signal (240) received from the combinational logic circuit's output (240). The accumulator (275) receives a control signal (280) and controls the phase of the synthesizer output (130) based upon the received control signal (280).
摘要翻译：公开了用于频率合成的系统和方法。数字频率合成器（105）的示例性实施例可以产生固定频率和/或调制信号（130）。示例性数字频率合成器包括串联耦合延迟单元（210），线性反馈移位寄存器（225）和累加器（275）。串联耦合延迟单元（210）从输入时钟信号（125）产生对应于分数时钟周期的多个时钟边沿（205）。线性反馈移位寄存器（225）基于从累加器（275）接收的符号/使能控制信号（230）和从接收到的累加器（275）接收的时钟信号（240），选择要传递到组合逻辑电路（255）的时钟边沿组合逻辑电路的输出（240）。累加器（275）接收控制信号（280），并基于所接收的控制信号（280）控制合成器输出（130）的相位。

108. 发明申请

WO2012040375A1 REGISTERS WITH FULL SCAN CAPABILITY 审中-公开
标题翻译：具有全扫描能力的注册
公开(公告)号：WO2012040375A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052629
申请日：2011-09-21
申请人： QUALCOMM Incorporated , RAO, Hari M. , YOON, Sei Seung , CHEN, Nan
发明人： RAO, Hari M. , YOON, Sei Seung , CHEN, Nan
IPC分类号： G11C29/32 , G01R31/3185
CPC分类号： G01R31/318541 , G11C11/417 , G11C29/32
摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.
摘要翻译：第一锁存器和第二锁存器的扫描测试将给定扫描值耦合到第一锁存器的输入，以将第一锁存器切换到与扫描值对应的状态，将扫描值从第一锁存器解耦合以锁定第一锁存器在该状态下锁存，将锁定在该状态的第一锁存器的输出耦合到第二锁存器的输入，以将第二锁存器切换到该状态，以及将第一锁存器的输出与第二锁存器的输入端分离在该状态下的第二个闩锁。

109. 发明申请

WO2012037338A1 INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES 审中-公开
标题翻译：使用增强型GATE-Q扫描技术的集成电路漏电功率降低
公开(公告)号：WO2012037338A1
公开(公告)日：2012-03-22
申请号：PCT/US2011/051745
申请日：2011-09-15
申请人： QUALCOMM INCORPORATED , SETHURAM, Rajamani , ARABI, Karim
发明人： SETHURAM, Rajamani , ARABI, Karim
IPC分类号： G01R31/3183 , G01R31/3185
CPC分类号： H03K19/0008 , G01R31/318342 , G01R31/318575 , G06F17/50 , H03K19/173
摘要： Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
摘要翻译：通过确定电路设计的最小泄漏状态，然后选择将电路设计保持在其最低泄漏状态的逻辑门来选择用于q门控的特定逻辑门。根据实现最小泄漏状态所需的输入，栅极可以选择为NOR或或门。在选择的操作模式期间可以启用用于实现最小泄漏状态的门实现的Q门控。电路的最小泄漏状态可以用自动测试图形生成（ATPG）工具确定。

110. 发明申请

WO2012027423A2 WIDE INPUT OUTPUT MEMORY WITH LOW DENSITY, LOW LATENCY AND HIGH DENSITY, HIGH LATENCY BLOCKS 审中-公开
标题翻译：宽输入输出存储器，低密度，低密度和高密度，高延迟块
公开(公告)号：WO2012027423A2
公开(公告)日：2012-03-01
申请号：PCT/US2011/048885
申请日：2011-08-24
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
发明人： GU, Shiqun , NOWAK, Matthew, M. , SRINIVASAN, Anand
IPC分类号： H01L23/48 , G11C11/4076
CPC分类号： G11C11/4076 , H01L23/481 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/00012 , H01L2924/00
摘要： External memory having a high density, high latency memory block; and a low density, low latency memory block. The two memory blocks may be separately accessed by one or more processing functional units. The access may be a direct memory access, or by way of a bus or fabric switch. Through-die vias may connect the external memory to a die comprising the one or more processing functional units.
摘要翻译：具有高密度，高延迟的存储器块的外部存储器; 和低密度，低延迟的存储器块。两个存储器块可以被一个或多个处理功能单元单独访问。访问可以是直接存储器访问，或者通过总线或结构交换机。通孔通孔可以将外部存储器连接到包括一个或多个处理功能单元的管芯。

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