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1. 发明申请

US20050264319A1 Low voltage high-speed differential logic devices and method of use thereof 有权
标题翻译：低电压高速差分逻辑器件及其使用方法
公开(公告)号：US20050264319A1
公开(公告)日：2005-12-01
申请号：US10857238
申请日：2004-05-28
申请人： Daniel Kucharski , Kevin Kornegay
发明人： Daniel Kucharski , Kevin Kornegay
IPC分类号： H03K3/2885 , H03K17/62 , H03K19/00 , H03K19/0175 , H03K19/086 , H03K19/20 , H03K19/21
CPC分类号： H03K3/2885 , H03K17/6264 , H03K19/001 , H03K19/086 , H03K19/212
摘要： A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%-50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.
摘要翻译：公开了一种用于高速低电压逻辑电路的电路拓扑，其将堆叠的有源电路元件的电平数量从3减少到2.提供了各种逻辑功能的电路，包括锁存器，异或门，组合XOR 并锁存，复用器和解复用器。根据本发明的原理构建的电路已经以40GHz的速度运行。电路拓扑可以在低至2V的电源电压（基于硅或硅锗器件）下工作，并且可根据逻辑功能提供25％-50％以上的功率节省。在一些实施例中，可以提供包括单端或差分输入的电路。

2. 发明授权

US5754062A Current switching logic type circuit with small current consumption 失效
标题翻译：电流开关逻辑电路，电流消耗小
公开(公告)号：US5754062A
公开(公告)日：1998-05-19
申请号：US735834
申请日：1996-10-23
申请人： Hisayasu Satoh , Kimio Ueda , Nagisa Sasaki
发明人： Hisayasu Satoh , Kimio Ueda , Nagisa Sasaki
IPC分类号： H03K3/2885 , H03K3/289 , H03K19/013 , H03K19/086 , H03K19/01
CPC分类号： H03K3/2885 , H03K19/0136 , H03K19/086 , H03K3/289
摘要： First emitters of a pair of input multi-emitter transistors are connected to a current source in common, to form an input differential amplifier. The other emitters of the input multi-emitter transistors are connected to current sources respectively. Pull-up and pull-down transistors are provided for respective ones of a pair of output terminals. Bases of the pull-up transistors are supplied with collector voltages of the input multi-emitter transistors, while those of the pull-down transistors are supplied with voltages of the other emitters of the multi-emitter transistors. Provided is an emitter-coupled logic circuit which has excellent load drivability, operates stably and obtains complementary outputs at a low cost.
摘要翻译：一对输入多发射极晶体管的第一发射极共同连接到电流源，以形成输入差分放大器。输入多发射极晶体管的其他发射极分别连接到电流源。为一对输出端子中的相应的一个提供了上拉和下拉晶体管。上拉晶体管的基极被提供有输入多发射极晶体管的集电极电压，而下拉晶体管的基极被提供多个发射极晶体管的其它发射极的电压。提供了一种发射极耦合逻辑电路，具有出色的负载驱动能力，稳定运行，并以低成本获得互补输出。

3. 发明授权

US5359241A ECL circuit 失效
标题翻译： ECL电路
公开(公告)号：US5359241A
公开(公告)日：1994-10-25
申请号：US54192
申请日：1993-04-30
申请人： Koichi Hasegawa , Tetsuya Iga
发明人： Koichi Hasegawa , Tetsuya Iga
IPC分类号： H03K3/286 , H03K3/012 , H03K3/2885 , H03K19/086 , H03K19/0175
CPC分类号： H03K3/2885 , H03K3/012
摘要： A flip-flop circuit of ECL structure includes an ECL circuit portion and a level shift circuit portion including a circuit having a pair of resistors. The ECL circuit portion applies a differential signal to one end of each of the resistors, and Q and/Q output signals are derived from the other ends of each of the resistors. The amount of level shift down of the signals when shifted by the resistors is enabled to be set to any relatively small amount, whereby the ECL circuit is permitted to operate at a low voltage.
摘要翻译： ECL结构的触发器电路包括ECL电路部分和包括具有一对电阻器的电路的电平移位电路部分。 ECL电路部分将差分信号施加到每个电阻器的一端，并且从每个电阻器的另一端导出Q和/ Q输出信号。当由电阻器移位时信号的电平偏移量能够被设置为任何相对较小的量，由此ECL电路被允许在低电压下操作。

4. 发明授权

US5334887A ECL latch circuit 失效
标题翻译： ECL锁存电路
公开(公告)号：US5334887A
公开(公告)日：1994-08-02
申请号：US60851
申请日：1993-05-12
申请人： Yasumi Kurashima
发明人： Yasumi Kurashima
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/20 , H03K3/01
CPC分类号： H03K3/2885
摘要： An ECL latch circuit includes a logic section and has a reset or set function. The logic section includes a first to seventh transistors. The third transistor has a collector connected to the collector of the first transistor, and a base for receiving a first reference potential or the collector potential of the second transistor through an emitter follower section. The fourth transistor has a collector connected to the collector of the second transistor, a base for receiving a collector potential of the first transistor through an emitter follower section or receiving a first reference potential, and an emitter connected to the emitter of the third transistor. The fifth transistor has a collector connected to the collector of the second or first transistor, a base for receiving a reset or set signal, and an emitter connected to the emitter of the third transistor.
摘要翻译： ECL锁存电路包括逻辑部分并具有复位或置位功能。逻辑部分包括第一至第七晶体管。第三晶体管具有连接到第一晶体管的集电极的集电极，以及用于通过射极跟随器部分接收第一参考电位或第二晶体管的集电极电位的基极。第四晶体管具有连接到第二晶体管的集电极的集电极，用于通过射极跟随器部分接收第一晶体管的集电极电位或接收第一参考电位的基极，以及连接到第三晶体管的发射极的发射极。第五晶体管具有连接到第二或第一晶体管的集电极的集电极，用于接收复位或置位信号的基极和连接到第三晶体管的发射极的发射极。

5. 发明授权

US5218249A High speed, low forward voltage drop, SCR 失效
标题翻译：高速，低正向压降，SCR
公开(公告)号：US5218249A
公开(公告)日：1993-06-08
申请号：US755081
申请日：1991-09-05
申请人： Mark Jordan
发明人： Mark Jordan
IPC分类号： H03K3/287 , H03K3/2885
CPC分类号： H03K3/2885 , H03K3/287
摘要： A silicon controlled rectifier device including an SCR portion controlled by an input voltage signal to a voltage comparator and having a latching circuit to permit the SCR portion to remain in the conducting state once switched even in the absence of the input voltage signal. Such a device is especially useful when a narrow input voltage signal is used to switch the SC portion into its conducting state.
摘要翻译：一种可控硅整流器件，其包括由输入电压信号控制到电压比较器的SCR部分，并且具有锁存电路，以允许SCR部分即使在没有输入电压信号的情况下也保持在导通状态。当使用窄输入电压信号将SC部分切换到其导通状态时，这种装置是特别有用的。

6. 发明授权

US5122682A Source-coupled FET-logic-type logic circuit 失效
标题翻译：源极耦合FET逻辑型逻辑电路
公开(公告)号：US5122682A
公开(公告)日：1992-06-16
申请号：US593041
申请日：1990-10-05
申请人： Hironori Nagasawa
发明人： Hironori Nagasawa
IPC分类号： H03K3/3562 , H03K3/2885 , H03K3/356 , H03K19/0952
CPC分类号： H03K3/2885 , H03K3/356034
摘要： A source-coupled FET-logic-type logic circuit having level shift elements connected to a high-potential power supply, field-effect transistors, load elements connecting the sources of the field-effect transistors, field-effect transistors coupled between the high-pontential power supply and a low-potential power supply, constant current sources, and complementary output terminals. The circuit further has a field-effect transistors controlled by complementary signals input to two input terminals. The circuit, which is a T flip-flop, further comprises a frequency switching circuit composed of field-effect transistors which are controlled by the signals supplied to two switching terminals. When the first switching terminal is at a high level, the output terminals outputs a signal having the same frequency as the input signal. When the first switching terminal is at a low level, the output terminals outputs a signal having half the frequency of the input signal.

7. 发明授权

US5086414A Semiconductor device having latch means 失效
标题翻译：具有锁存装置的半导体装置
公开(公告)号：US5086414A
公开(公告)日：1992-02-04
申请号：US436770
申请日：1989-11-15
申请人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
发明人： Hiroaki Nambu , Noriyuki Homma , Kunihiko Yamaguchi , Kazuo Kanetani , Youji Idei , Kenichi Ohhata , Yoshiaki Sakurai , Jun Etoh
IPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356
CPC分类号： G11C7/22 , G11C8/18 , H03K3/2885 , H03K3/356113 , H03K3/356156
摘要： A semiconductor circuit having a plurality of circuit blocks, each having latch circuits each one thereof being controlled by an internally provided clock signal for preventing malfunction of the circuit. Each circuit is provided with the latch function so that the cycle time is made shorter than the access time. Moreover, the latch means are driven in such a manner that the adjoining ones are prevented from being put to through-state simultaneously, whereby malfunction is prevented.
摘要翻译：具有多个电路块的半导体电路，每个具有锁存电路，每个电路块由内部提供的时钟信号控制，用于防止电路的故障。每个电路都具有锁存功能，使得周期时间短于访问时间。此外，锁定装置被驱动，使得相邻的锁定装置被阻止同时被置于通过状态，从而防止了故障。

8. 发明授权

US5068550A ECL-TTL signal level converter 失效
标题翻译： ECL-TTL信号电平转换器
公开(公告)号：US5068550A
公开(公告)日：1991-11-26
申请号：US594732
申请日：1990-10-09
申请人： Claude Barre
发明人： Claude Barre
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/013 , H03K19/018
CPC分类号： H03K19/01806 , H03K19/013 , H03K3/2885
摘要： An ECL-TTL signal level converter includes a first transistor pair having transistors controlled by ECL signals. A second transistor pair is connected to the transistors of the first transistor pair. Collector resistors are connected between the transistors of the second transistor pair and a first supply potential. A third transistor pair has transistors connected to the transistors of the first transistor pair. A fourth transistor pair has transistors connected to the transistors of the first transistor pair and to the transistors of the third transistor pair. A current impressing device is connected between the transistors of the fourth transistor pair and a second supply potential. A push-pull output stage is connected to the transistors of the second transistor pair for the emission of a TTL signal.
摘要翻译： ECL-TTL信号电平转换器包括具有由ECL信号控制的晶体管的第一晶体管对。第二晶体管对连接到第一晶体管对的晶体管。集电极电阻连接在第二晶体管对的晶体管和第一电源电位之间。第三晶体管对具有连接到第一晶体管对的晶体管的晶体管。第四晶体管对具有连接到第一晶体管对的晶体管和第三晶体管对的晶体管的晶体管。电流施加装置连接在第四晶体管对的晶体管和第二电源电位之间。推挽输出级连接到第二晶体管对的晶体管，用于发射TTL信号。

9. 发明授权

US4999520A High speed TTL buffer circuit which is resistive to the influence of alpha-rays 失效
标题翻译：高速TTL缓冲电路，可抵抗α射线的影响
公开(公告)号：US4999520A
公开(公告)日：1991-03-12
申请号：US330461
申请日：1989-03-30
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K3/2885 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K19/086
摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
摘要翻译：一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通的相分离电路。

10. 发明授权

US4943741A ECL/CML emitter follower current switch circuit 失效
标题翻译： ECL / CML射极跟随器电流开关电路
公开(公告)号：US4943741A
公开(公告)日：1990-07-24
申请号：US356785
申请日：1989-05-24
申请人： Julio R. Estrada , Roy L. Yarbrough
发明人： Julio R. Estrada , Roy L. Yarbrough
IPC分类号： G11C11/416 , H03K3/2885 , H03K17/66 , H03K19/086
CPC分类号： H03K17/662 , H03K17/66 , H03K3/2885
摘要： An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively. Cross control circuits are provided so that the current switch transistor element for the true output is controlled by the complementary output signal potential level and the current switch transistor element for the complementary output is controlled by the true output signal potential level.

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