专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4943741A ECL/CML emitter follower current switch circuit 失效
标题翻译： ECL / CML射极跟随器电流开关电路
公开(公告)号：US4943741A
公开(公告)日：1990-07-24
申请号：US356785
申请日：1989-05-24
申请人： Julio R. Estrada , Roy L. Yarbrough
发明人： Julio R. Estrada , Roy L. Yarbrough
IPC分类号： G11C11/416 , H03K3/2885 , H03K17/66 , H03K19/086
CPC分类号： H03K17/662 , H03K17/66 , H03K3/2885
摘要： An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively. Cross control circuits are provided so that the current switch transistor element for the true output is controlled by the complementary output signal potential level and the current switch transistor element for the complementary output is controlled by the true output signal potential level.

2. 发明授权

US5508702A BiCOMS digital-to-analog conversion 失效
标题翻译： BiCOMS数模转换
公开(公告)号：US5508702A
公开(公告)日：1996-04-16
申请号：US261716
申请日：1994-06-17
申请人： Julio R. Estrada , Ray A. Mentzer
发明人： Julio R. Estrada , Ray A. Mentzer
IPC分类号： H03M1/74 , H03M1/80
CPC分类号： H03M1/745
摘要： A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay. The introduction of bipolar transistor devices to regulate the source and control nodes of the MOS output transistors utilizes the best characteristics of both transistor types to enhance converter monotonicity and linearity, in addition to reducing noise.
摘要翻译：具有一个或多个转换单元的数模转换装置，每个单元耦合到主电压源和特定的二进制输入元件。转换单元包括二进制加权或二进制尺寸的输出晶体管，使得当被调用时，每个输出晶体管提供对应于特定二进制信号的唯一模拟输出电流。由稳定源提供的主电位被提供给输出晶体管的控制节点，使得那些控制节点处的电位保持不变。通过调节这些晶体管的源极而不是其栅极来实现输出晶体管的接通和关断。通过调节输出晶体管在其源极的操作，本发明提供了一种数模转换器和具有很小开关噪声和最小开关延迟的转换方法。引入双极晶体管器件来调节MOS输出晶体管的源极和控制节点除了降低噪声之外，还利用了两种晶体管类型的最佳特性来提高转换器单调性和线性度。

3. 发明授权

US5382921A Automatic selection of an operating frequency in a low-gain broadband phase lock loop system 失效
标题翻译：在低增益宽带锁相环系统中自动选择工作频率
公开(公告)号：US5382921A
公开(公告)日：1995-01-17
申请号：US984172
申请日：1992-11-23
申请人： Julio R. Estrada , Ray A. Mentzer
发明人： Julio R. Estrada , Ray A. Mentzer
IPC分类号： H03K3/03 , H03L7/089 , H03L7/099 , H03L7/00
CPC分类号： H03L7/089 , H03K3/0315 , H03L7/0997
摘要： A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.
摘要翻译：一种宽带低增益系统，用于自动对系统使用数字和模拟设备和技术的信号进行频率锁定。该系统包括比较器，上/下计数器，数模转换器，解码器，环形振荡器和下降计数器。数字控制信号由解码器提供并且致动多个环形振荡器级之一。模拟控制信号由数模转换器提供，并且在致动级中控制微调机构。该系统包括用于清除计数器的主复位。

4. 发明授权

US5101124A ECL to TTL translator circuit with improved slew rate 失效
标题翻译： ECL到TTL转换器电路，具有改进的转换速率
公开(公告)号：US5101124A
公开(公告)日：1992-03-31
申请号：US639793
申请日：1991-01-10
申请人： Julio R. Estrada
发明人： Julio R. Estrada
IPC分类号： H03K19/013 , H03K19/018
CPC分类号： H03K19/01812 , H03K19/0136
摘要： An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V.sub.IN) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V.sub.OUT) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V.sub.OUT). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element. The first emitter follower output circuit (Q7, Q8, R4) is coupled to the base node (C) of voltage amplifier transistor element (Q6) and the second emitter follower output circuit (Q3, Q4, R3) is coupled to the collector node (D) of the voltage amplifier transistor element (Q6) for controlling the conducting state of (Q6) in accordance with ECL input signals and for effecting translation with improved output switching speed.
摘要翻译： ECL到TTL转换器电路包括ECL输入门，TTL输出门和耦合在ECL输入门和TTL输出门之间的电压放大器晶体管元件电路，用于进行翻译。 ECL门具有差分ECL输入，用于至少在ECL输入（VIN）和差分第一和第二ECL输出节点（A，B）之一处接收ECL输入信号。第一和第二射极跟随器输出电路（Q7，Q3）耦合到相应的第一和第二ECL输出节点（A，B）。 TTL门（12）具有TTL输出（VOUT），用于传送对应于ECL输入信号的TTL输出信号。 TTL门极分相晶体管元件（Q9）控制TTL输出（VOUT）。电压放大器晶体管元件（Q6）的集电极节点耦合到相位分离器晶体管元件（Q9）的基极节点，用于控制与电压放大器晶体管元件异相的分相器晶体管元件的导通状态。第一射极跟随器输出电路（Q7，Q8，R4）耦合到电压放大器晶体管元件（Q6）的基极节点（C），第二射极跟随器输出电路（Q3，Q4，R3）耦合到收集器节点用于根据ECL输入信号控制（Q6）的导通状态的电压放大器晶体管元件（Q6）的（D）和用于以改善的输出开关速度进行平移。

5. 发明授权

US5051623A TTL tristate circuit for output pulldown transistor 失效
标题翻译： TTL三态电路，用于输出下拉晶体管
公开(公告)号：US5051623A
公开(公告)日：1991-09-24
申请号：US537903
申请日：1990-06-16
申请人： Roy L. Yarbrough , Julio R. Estrada
发明人： Roy L. Yarbrough , Julio R. Estrada
IPC分类号： H03K17/04 , H03K19/013 , H03K19/0175 , H03K19/082 , H03K19/088
CPC分类号： H03K19/013 , H03K19/0826
摘要： The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver. The emitter follower DCMK signal output and voltage divider coupling reduce DCMK signal generation delay, eliminate current hogging between Miller killer transistor elements of the multiple output buffers of a multi-bit output, and dispense with the ballast resistors which introduce delay.
摘要翻译：用于TTL三态输出缓冲器电路的较低输出下拉三态电路包括具有＆amp; O和O信号输入的使能信号反相器缓冲器和提供输出使能OE信号的OE信号输出，以及具有耦合在 TTL三态输出下拉晶体管的基极节点和低电位电源轨。发射极跟随器晶体管元件的基极节点连接到＆Upbar＆O信号输入端，发射极节点提供与上拉和O信号输入同相的DC Miller杀手DCMK信号输出。分压器将DCMK信号输出端耦合到Miller抑制晶体管元件的基极节点，用于在输出端的高阻抗三态期间响应于高电位DCMK信号而放电输出下拉晶体管的基极。 DC Miller杀手电路应用于高速TTL三态输出和多位线驱动器。射极跟随器DCMK信号输出和分压器耦合降低了DCMK信号产生延迟，消除了多位输出的多输出缓冲器的米勒杀伤晶体管元件之间的电流占空比，并且省去了引入延迟的镇流电阻。

6. 发明授权

US4972104A TTL totem pole anti-simultaneous conduction circuit 失效
标题翻译： TTL图腾柱反同步传导电路
公开(公告)号：US4972104A
公开(公告)日：1990-11-20
申请号：US202971
申请日：1988-06-03
申请人： Julio R. Estrada
发明人： Julio R. Estrada
IPC分类号： H03K17/16 , H03K17/66 , H03K19/00 , H03K19/018 , H03K19/088
CPC分类号： H03K19/088 , H03K19/001
摘要： An anti-simultaneous conduction transistor is incorporated into the standard TTL circuit totem pole to reduce simultaneous conduction of the pullup and pulldown transistor elements of the totem pole. The collector of the active discharge anti-simultaneous conduction transistor element (Q5) is operatively coupled to a base of the pullup transistor element (Q2,Q3) through a diode (D5), the emitter is coupled to low potential, and the base is coupled to the base of the pulldown transistor element (Q4) through ballast resistance (R6,R7). The anti-simultaneous conduction transistor element (Q5) mirrors the conducting state of the pulldown transistor element (Q4) without current hogging substantially diverting or discharging base current from the base of the pullup transistor element (Q2,Q3) whenever the pulldown transistor element (Q4) is conducting. Undesirable current spikes in the sourcing current are avoided by preventing simultaneous conduction in the totem pole.

7. 发明授权

US4945265A ECL/CML pseudo-rail circuit, cutoff driver circuit, and latch circuit 失效
标题翻译： ECL / CML伪轨电路，截止驱动电路和锁存电路
公开(公告)号：US4945265A
公开(公告)日：1990-07-31
申请号：US379088
申请日：1989-07-13
申请人： Julio R. Estrada
发明人： Julio R. Estrada
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/00 , H03K19/086
CPC分类号： H03K3/2885 , H03K19/001 , H03K19/086
摘要： A pseudo-rail circuit is coupled between the differential output gate or buffer of an emitter coupled logic or current mode logic (ECL/CML) circuit and the high potential level power rail. The pseudo-rail circuit provides a pseudo-rail node. A first clamp circuit is coupled to the pseudo-rail node for clamping the pseudo-rail node at a first potential level in response to a first control signal. A second clamp circuit is coupled to the pseudo-rail node for clamping at a second potential level in response to a second control signal. A clamp switching circuit alternately applies the first and second clamp circuits to the pseudo-rail node in response to the control signals. As a cutoff driver circuit, the first clamp circuit of the pseudo-rail circuit applies the high potential level of the power rail to the pseudo-rail node. The second claim circuit pulls down the pseudo-rail node to hold the output of the differential output gate in the cutoff state. An output enable (OE) differential gate or buffer provides the clamp switching circuit. The pseudo-rail circuit is incorporated directly in a latch circuit to initiate the cutoff state in response to an OE cutoff signal without losing latched data and without requiring an additional output buffer stage.

8. 发明授权

US4945263A TTL to ECL/CML translator circuit with differential output 失效
标题翻译： TTL到具有差分输出的ECL / CML转换器电路
公开(公告)号：US4945263A
公开(公告)日：1990-07-31
申请号：US397769
申请日：1989-08-23
申请人： Julio R. Estrada
发明人： Julio R. Estrada
IPC分类号： H03K19/018
CPC分类号： H03K19/01812
摘要： A TTL to ECL/CML translator circuit delivers differential or complementary ECL logic output signals in response to TTL input signals with voltage gain, small output voltage swing and with a narrow transition region. The TTL input circuit is coupled to a current mirror circuit with first and second current mirror branch circuits. A differential amplifier gate circuit with differential amplifier first and second gate transistor elements co-acts with the current mirror circuit. The second current mirror branch circuit also constitutes the differential amplifier first gate transistor element. A threshold clamp circuit applies a threshold voltage level at the base node of the differential amplifier second gate transistor element thereby establishing a TTL input threshold at the threshold voltage level. First and second ECL output circuits are coupled to the collector nodes of the differential amplifier first and second gate transistor elements for delivering complementary ECL output signals. The biasing components or elements of the TTL input circuit and threshold clamp circuit are selected for example for an output voltage swing of 1V.sub.BE, a threshold voltage level of 2V.sub.BE, and so that the voltage level at a common emitter node coupling of the current mirror circuit and differential amplifier gate circuit rises to turn off the second gate transistor element when the current mirror is conducting.

9. 发明授权

US5013938A ECL cutoff driver circuit with reduced stanby power dissipation 失效
标题翻译： ECL截止驱动电路具有降低的稳定功耗
公开(公告)号：US5013938A
公开(公告)日：1991-05-07
申请号：US430431
申请日：1989-11-01
申请人： Julio R. Estrada
发明人： Julio R. Estrada
IPC分类号： H03K19/00 , H03K19/086
CPC分类号： H03K19/086 , H03K19/0016
摘要： The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit provides the OE signals of high and low potential to the OE cutoff driver gate. The OE cutoff driver current sink for sinking current from the OE cutoff driver gate is provided by a current switch circuit for switching sinking current on and off in response to current switch signals of high and low potential in phase with the OE signals. The current switch circuit switches on sinking current when the OE cutoff driver gate is holding the ECL logic gate in the cutoff state. The current switch circuit switches off sinking current for reducing power dissipation when the ECL logic gate is out of the cutoff state. The current switch circuit is provided by a current mirror circuit. A first emitter follower output buffer delivers OE signals from an OE input gate to the OE cutoff driver gate. A second emitter follower output buffer delivers current switch signals from the OE input gate to the current mirror circuit in phase with the OE signals.

10. 发明授权

US4947058A TTL current sinking circuit with transient performance enhancement during output transition from high to low 失效
标题翻译： TTL电流吸收电路在输出从高电平变为低电平期间具有瞬态性能增强
公开(公告)号：US4947058A
公开(公告)日：1990-08-07
申请号：US202237
申请日：1988-06-03
申请人： Roy L. Yarbrough , Julio R. Estrada
发明人： Roy L. Yarbrough , Julio R. Estrada
IPC分类号： H03K19/088 , H03K17/04 , H03K19/013
CPC分类号： H03K19/0136
摘要： A transient voltage difference circuit is coupled into a TTL current sinking output circuit for transient performance enhancement during transition from high to low level potential at the output. The TTL output circuit includes a pulldown transistor element for sinking current from an output node to low potential, a base drive transistor for driving the base of a current sinking pulldown transistor element, an input base node of the base drive transistor coupled to receive input signals of high and low level potential, and a voltage clamp network coupled between the input base node and low potential for maintaining a potential level at the input base node sufficient to turn on the base drive transistor. An RC network is coupled between the input base node and low potential. The resistance of the RC network is coupled in series with the voltage clamping network adding a transient overdrive voltage in series with the clamping voltage at the input base node when the capacitance of the RC network is charging through the resistance during transition from low to high level potential at the input. The RC network and the voltage clamp network effectively form a Y network with the common branch coupled to the input base node through the resistance.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式