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1. 发明申请

US20150171864A1 BIPOLAR-MOS MEMORY CIRCUIT 有权
标题翻译：双极MOS存储器电路
公开(公告)号：US20150171864A1
公开(公告)日：2015-06-18
申请号：US14628925
申请日：2015-02-23
申请人： Daniel R. Shepard
发明人： Daniel R. Shepard
IPC分类号： H03K19/00 , H03K19/0948 , H03K19/082 , G11C5/06
CPC分类号： H03K19/0013 , G11C5/06 , G11C11/06007 , G11C11/22 , G11C11/4097 , G11C11/412 , H01L29/66234 , H03K19/001 , H03K19/082 , H03K19/094 , H03K19/0948
摘要： The present invention relates to electronic memory circuits, and more particularly, to low power electronic memory circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
摘要翻译：电子存储器电路技术领域本发明涉及电子存储器电路，更具体地涉及低成本的低功率电子存储器电路。本发明是利用双极和MOS（但不是NMOS和PMOS两者）的两种晶体管类型的电路设计，其中一个可以与存储单元的非线性导电元件（例如二极管）一起制造，从而减少加工步骤和掩模的数量，并导致较低的成本。

2. 发明申请

US20140160827A1 Bipolar-MOS Memory Circuit 有权
标题翻译：双极MOS存储器电路
公开(公告)号：US20140160827A1
公开(公告)日：2014-06-12
申请号：US13714499
申请日：2012-12-14
申请人： Daniel Robert Shepard
发明人： Daniel Robert Shepard
IPC分类号： H01L29/66 , G11C5/06
CPC分类号： H03K19/0013 , G11C5/06 , G11C11/06007 , G11C11/22 , G11C11/4097 , G11C11/412 , H01L29/66234 , H03K19/001 , H03K19/082 , H03K19/094 , H03K19/0948
摘要： The present invention relates to electronic memory circuits, and more particularly, to low power electronic memory circuits having low manufacturing costs. The present invention is a circuit design that utilizes two transistor types—bipolar and MOS (but, not both NMOS and PMOS) one of which can be manufactured together with the memory cell's non-linear conductive elements (such as a diode) thereby reducing the number of processing steps and masks and resulting in lower cost.
摘要翻译：电子存储器电路技术领域本发明涉及电子存储器电路，更具体地涉及低成本的低功率电子存储器电路。本发明是利用双极和MOS（但不是NMOS和PMOS两者）的两种晶体管类型的电路设计，其中一个可以与存储单元的非线性导电元件（例如二极管）一起制造，从而减少加工步骤和掩模的数量，并导致较低的成本。

3. 发明授权

US08680885B1 Low leakage logic circuit 有权
标题翻译：低泄漏逻辑电路
公开(公告)号：US08680885B1
公开(公告)日：2014-03-25
申请号：US13686002
申请日：2012-11-27
申请人： Valter Karavanic , Gary Hau
发明人： Valter Karavanic , Gary Hau
IPC分类号： H03K17/16 , H03K19/003 , H03K19/23
CPC分类号： H03K19/001 , H03K19/00392
摘要： A low leakage logic circuit. The low leakage logic circuit includes a control circuit for logic circuit. The control circuit has a first transistor, a second transistor, a third transistor, a first diode, a first resistor and a second resistor. When the control circuit is ON, a first circuit path in the logic circuit is supplied with a first voltage from the source terminal of the third transistor. This voltage acts as a logic output and has the ability to source current at output terminal of the logic circuit. When the control circuit is OFF, a second circuit path in the logic circuit is supplied with a second voltage from the control circuit which is lower than the turn-on voltage of the second circuit path. This voltage is insufficient to turn ON the logic circuit, hence no current flows into the logic circuit.
摘要翻译：低泄漏逻辑电路。低泄漏逻辑电路包括用于逻辑电路的控制电路。控制电路具有第一晶体管，第二晶体管，第三晶体管，第一二极管，第一电阻器和第二电阻器。当控制电路为ON时，从第三晶体管的源极端子向逻辑电路中的第一电路提供第一电压。该电压用作逻辑输出，并具有在逻辑电路的输出端输出电流的能力。当控制电路断开时，向控制电路提供逻辑电路中的第二电路，该第二电压低于第二电路路径的接通电压。该电压不足以导通逻辑电路，因此没有电流流入逻辑电路。

4. 发明授权

US08410817B2 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US08410817B2
公开(公告)日：2013-04-02
申请号：US12858295
申请日：2010-08-17
申请人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
发明人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
IPC分类号： H03K19/0175 , H03B1/00
CPC分类号： H03K19/001 , H03K17/04126 , H03K19/0136 , H03K2217/0036
摘要： A level switch circuit receives a digital input signal, and generates a level signal having a voltage level that corresponds to the value of the input signal thus received. A buffer circuit receives a level signal, and outputs the level signal via an output terminal thereof. A bias current generating circuit generates a bias current including a DC component having a constant level and a variable component that changes according to the input signal, and supplies the bias current thus generated to a buffer circuit. The bias current generating circuit detects an edge of the input signal, and raises the bias current by a predetermined amount for a predetermined period of time after the edge thus detected.
摘要翻译：电平开关电路接收数字输入信号，并产生具有与所接收的输入信号的值对应的电压电平的电平信号。缓冲电路接收电平信号，并通过其输出端输出电平信号。偏置电流产生电路产生包括具有恒定电平的DC分量和根据输入信号而变化的可变分量的偏置电流，并将由此产生的偏置电流提供给缓冲电路。偏置电流产生电路检测输入信号的边缘，并且在如此检测到的边缘之后的预定时间段内将偏置电流提高预定量。

5. 发明申请

US20080231322A1 Circuit Device and Method of Controlling a Voltage Swing 有权
标题翻译：控制电压摆动的电路装置及方法
公开(公告)号：US20080231322A1
公开(公告)日：2008-09-25
申请号：US11843696
申请日：2007-08-23
申请人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
发明人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译：在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。该方法包括在包括电容性节点的数字电路装置的输入处接收信号。该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。在特定说明性实施例中，接收信号可以是时钟信号。

6. 发明授权

US07327164B2 Interface circuit 有权
标题翻译：接口电路
公开(公告)号：US07327164B2
公开(公告)日：2008-02-05
申请号：US11348462
申请日：2006-02-07
申请人： Jianqin Wang
发明人： Jianqin Wang
IPC分类号： H03K19/082 , H03K19/0175
CPC分类号： H03K19/001 , H03K19/01812
摘要： An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.
摘要翻译：接口电路包括第一和第二输入端，第一输出晶体管，第二输出晶体管，第一输出控制器，用于根据提供给第一和第二输入端的电压实现控制，使得预定电流出现在如果第一输出晶体管处于饱和状态，则第一输出晶体管的控制端子，并且如果第一输出晶体管处于截止状态，则将预定电流提供给第一输出晶体管的控制端子;以及第二输出控制器，用于根据提供给第一和第二输入端子的电压，使得如果第二输出晶体管处于饱和状态，则在第二输出晶体管的控制端子处出现预定电流，并且将预定电流提供给第二输出晶体管的控制端子，如果第二输出晶体管处于截止状态。

7. 发明申请

US20050264319A1 Low voltage high-speed differential logic devices and method of use thereof 有权
标题翻译：低电压高速差分逻辑器件及其使用方法
公开(公告)号：US20050264319A1
公开(公告)日：2005-12-01
申请号：US10857238
申请日：2004-05-28
申请人： Daniel Kucharski , Kevin Kornegay
发明人： Daniel Kucharski , Kevin Kornegay
IPC分类号： H03K3/2885 , H03K17/62 , H03K19/00 , H03K19/0175 , H03K19/086 , H03K19/20 , H03K19/21
CPC分类号： H03K3/2885 , H03K17/6264 , H03K19/001 , H03K19/086 , H03K19/212
摘要： A circuit topology for high speed low voltage logic circuits is disclosed that reduces the number of levels of stacked active circuit elements from 3 to 2. Circuits providing a variety of logic functions are presented, including a latch, an exclusive OR gate, a combination XOR and latch, a multiplexer and a demultiplexer. Circuits built according to the principles of the invention have been operated at speeds of 40 GHz. The circuit topology can operate at supply voltages as low as 2V (for silicon or silicon-germanium based devices) and provide power saving of 25%-50% or more, depending on the logic function. In some embodiments, circuits comprising single ended or differential inputs can be provided.
摘要翻译：公开了一种用于高速低电压逻辑电路的电路拓扑，其将堆叠的有源电路元件的电平数量从3减少到2.提供了各种逻辑功能的电路，包括锁存器，异或门，组合XOR 并锁存，复用器和解复用器。根据本发明的原理构建的电路已经以40GHz的速度运行。电路拓扑可以在低至2V的电源电压（基于硅或硅锗器件）下工作，并且可根据逻辑功能提供25％-50％以上的功率节省。在一些实施例中，可以提供包括单端或差分输入的电路。

8. 发明授权

US6091266A Circuit arrangement for a digital circuit using differential logic 失效
标题翻译：使用差分逻辑的数字电路的电路布置
公开(公告)号：US6091266A
公开(公告)日：2000-07-18
申请号：US150689
申请日：1998-09-10
申请人： Wolfgang Pohlmann
发明人： Wolfgang Pohlmann
IPC分类号： H03K19/088 , H03K19/00 , H03K19/082
CPC分类号： H03K19/001
摘要： Circuits using differential logic are employed in high-speed optical communications systems. An essential problem in the design of large-scale integrated circuits for this purpose is the control of undesired heat generation, so that the circuits should have low power consumption. According to the invention, a reduction in power consumption is achieved by reducing the number of stages connected in parallel with respect to the power supply. To accomplish this, part of the parallel-connected stages are connected in series with the remaining part of the parallel-connected stages, so that the total number of parallel branches is reduced.
摘要翻译：在高速光通信系统中采用使用差分逻辑的电路。为此，设计大规模集成电路的一个基本问题是控制不需要的发热，因此电路应具有低功耗。根据本发明，通过减少相对于电源并联连接的级数来实现功耗的降低。为了实现这一点，部分并联级与并联级的剩余部分串联连接，从而减少并联分支的总数。

9. 发明授权

US5926040A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US5926040A
公开(公告)日：1999-07-20
申请号：US819394
申请日：1997-03-17
申请人： Kazunori Tsugaru
发明人： Kazunori Tsugaru
IPC分类号： H03K19/00 , H03K19/08 , H03K19/086
CPC分类号： H03K19/001 , H03K19/086
摘要： An Emitter Coupled Logic (ECL) circuit includes therein a constant potential generating circuit which is comprised of a load resistor, an active pull-down transistor and a constant current source. By containing the constant potential generating circuit which has been independently provided externally to an ECL circuit, the ECL logic circuit is operable at the power supply potential of -4.5 V or -5.2 V at the high speed with reduced power supply consumption. The constant current source is an NPN transistor whose base is connected to an output node of a bias circuit, and the output of the bias circuit is an output having a value set so that a collector current of the active pull-down transistor is kept constant at all times. Hence, the electric power consumption can be further reduced.
摘要翻译：发射极耦合逻辑（ECL）电路包括一个恒定电位产生电路，它包括负载电阻，有源下拉晶体管和恒流源。通过包含在ECL电路外部独立设置的恒定电位发生电路，ECL逻辑电路可以以-4.5V或-5.2V的电源电位在高速下工作，并且降低电源消耗。恒流源是NPN晶体管，其基极连接到偏置电路的输出节点，偏置电路的输出是具有设定值的输出，使得有源下拉晶体管的集电极电流保持恒定每时每刻。因此，可以进一步降低电力消耗。

10. 发明授权

US5041743A Emitter-follower circuit with reduced delay time 失效
标题翻译：发射器跟随器电路，延迟时间缩短
公开(公告)号：US5041743A
公开(公告)日：1991-08-20
申请号：US558308
申请日：1990-07-25
申请人： Kouji Matsumoto
发明人： Kouji Matsumoto
IPC分类号： H03K19/086 , H03K19/00 , H03K19/013
CPC分类号： H03K19/001 , H03K19/0136
摘要： The emitter-follower circuit of the invention, having a current-switching type logic circuit operating between the ground potential and the first negative power supply potential, comprises an emitter-follower transistor having its emitter connected to an output terminal; a first transistor having its collector connected to the ground potential; a second transistor having its base connected to the emitter of the first transistor and its emitter connected to the second negative power supply potential; and a diode connected between the base of the first transistor and the output terminal. The emitter-follower circuit may further comprises an input emitter-follower circuit stage and a differential circuit which make the speed of turn-off operation of the second transistor high. The second transistor receives at its base a signal whose phase is inverted with respect to the phase of the signal received by the emitter-follower transistor from the current-switching type logic circuit. In the transition of the output signal changing from its High to Low level, the second transistor serves to provide a current-path for discharging the charge which was charged in a capacitance of the load, whereby the delay time is shortened without a noise margin being decreased.

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