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1. 发明授权

US5051623A TTL tristate circuit for output pulldown transistor 失效
标题翻译： TTL三态电路，用于输出下拉晶体管
公开(公告)号：US5051623A
公开(公告)日：1991-09-24
申请号：US537903
申请日：1990-06-16
申请人： Roy L. Yarbrough , Julio R. Estrada
发明人： Roy L. Yarbrough , Julio R. Estrada
IPC分类号： H03K17/04 , H03K19/013 , H03K19/0175 , H03K19/082 , H03K19/088
CPC分类号： H03K19/013 , H03K19/0826
摘要： The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver. The emitter follower DCMK signal output and voltage divider coupling reduce DCMK signal generation delay, eliminate current hogging between Miller killer transistor elements of the multiple output buffers of a multi-bit output, and dispense with the ballast resistors which introduce delay.
摘要翻译：用于TTL三态输出缓冲器电路的较低输出下拉三态电路包括具有＆amp; O和O信号输入的使能信号反相器缓冲器和提供输出使能OE信号的OE信号输出，以及具有耦合在 TTL三态输出下拉晶体管的基极节点和低电位电源轨。发射极跟随器晶体管元件的基极节点连接到＆Upbar＆O信号输入端，发射极节点提供与上拉和O信号输入同相的DC Miller杀手DCMK信号输出。分压器将DCMK信号输出端耦合到Miller抑制晶体管元件的基极节点，用于在输出端的高阻抗三态期间响应于高电位DCMK信号而放电输出下拉晶体管的基极。 DC Miller杀手电路应用于高速TTL三态输出和多位线驱动器。射极跟随器DCMK信号输出和分压器耦合降低了DCMK信号产生延迟，消除了多位输出的多输出缓冲器的米勒杀伤晶体管元件之间的电流占空比，并且省去了引入延迟的镇流电阻。

2. 发明授权

US4943741A ECL/CML emitter follower current switch circuit 失效
标题翻译： ECL / CML射极跟随器电流开关电路
公开(公告)号：US4943741A
公开(公告)日：1990-07-24
申请号：US356785
申请日：1989-05-24
申请人： Julio R. Estrada , Roy L. Yarbrough
发明人： Julio R. Estrada , Roy L. Yarbrough
IPC分类号： G11C11/416 , H03K3/2885 , H03K17/66 , H03K19/086
CPC分类号： H03K17/662 , H03K17/66 , H03K3/2885
摘要： An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively. Cross control circuits are provided so that the current switch transistor element for the true output is controlled by the complementary output signal potential level and the current switch transistor element for the complementary output is controlled by the true output signal potential level.

3. 发明授权

US4947058A TTL current sinking circuit with transient performance enhancement during output transition from high to low 失效
标题翻译： TTL电流吸收电路在输出从高电平变为低电平期间具有瞬态性能增强
公开(公告)号：US4947058A
公开(公告)日：1990-08-07
申请号：US202237
申请日：1988-06-03
申请人： Roy L. Yarbrough , Julio R. Estrada
发明人： Roy L. Yarbrough , Julio R. Estrada
IPC分类号： H03K19/088 , H03K17/04 , H03K19/013
CPC分类号： H03K19/0136
摘要： A transient voltage difference circuit is coupled into a TTL current sinking output circuit for transient performance enhancement during transition from high to low level potential at the output. The TTL output circuit includes a pulldown transistor element for sinking current from an output node to low potential, a base drive transistor for driving the base of a current sinking pulldown transistor element, an input base node of the base drive transistor coupled to receive input signals of high and low level potential, and a voltage clamp network coupled between the input base node and low potential for maintaining a potential level at the input base node sufficient to turn on the base drive transistor. An RC network is coupled between the input base node and low potential. The resistance of the RC network is coupled in series with the voltage clamping network adding a transient overdrive voltage in series with the clamping voltage at the input base node when the capacitance of the RC network is charging through the resistance during transition from low to high level potential at the input. The RC network and the voltage clamp network effectively form a Y network with the common branch coupled to the input base node through the resistance.

4. 发明申请

US20100060337A1 POWER SUPPLY INSENSITIVE VOLTAGE LEVEL TRANSLATOR 有权
标题翻译：电源电压电平转换器
公开(公告)号：US20100060337A1
公开(公告)日：2010-03-11
申请号：US12205178
申请日：2008-09-05
申请人： Hrvoje Jasa , Steven M. Macaluso , Julie Stultz , Roy L. Yarbrough
发明人： Hrvoje Jasa , Steven M. Macaluso , Julie Stultz , Roy L. Yarbrough
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.
摘要翻译：描述了一种电路，当控制通过晶体管的电路的电源为零电压时，配置为电压电平转换器的通过晶体管将保持关断，而不管连接到传输晶体管的端口处的电压和电压变化。交叉耦合晶体管提供了一种机制，其中较高的端口电压可用于将通态晶体管的控制输入保持在关闭状态的电源电路。端口处的电压可以相对于彼此上升和下降，但是传输晶体管的控制输入将保持传输晶体管关闭。

5. 发明授权

US5521789A BICMOS electrostatic discharge protection circuit 失效
标题翻译： BICMOS静电放电保护电路
公开(公告)号：US5521789A
公开(公告)日：1996-05-28
申请号：US213661
申请日：1994-03-15
申请人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An enhanced bipolar-transistor apparatus for protecting electronic devices from electrostatic discharge damage. The apparatus is built around a bipolar transistor coupled between a power rail and the circuit to be protected. The protection is based on the high-current-capacity path through the bipolar transistor which is opened up either by collector-to-emitter punch-through in the bipolar transistor or by the bipolar transistor going into normal conduction upon being turned on by a switch coupled to the base of the bipolar transistor. In the preferred embodiment the switch is a MOS transistor that is designed to undergo source-to-drain breakdown at a fixed threshold voltage, whereupon it activates the bipolar transistor which in turn discharges the overvoltage. In this way the advantages of the high-current-capacity bipolar transistor are obtained without the concern that fabrication vagaries will prevent the bipolar transistor from providing needed protection, such as is the situation where the punch-through phenomenon alone is relied on.
摘要翻译：一种用于保护电子器件免受静电放电损坏的增强型双极晶体管装置。该装置围绕耦合在电源轨和待保护电路之间的双极晶体管构成。该保护基于通过双极晶体管的大电流容量路径，其通过双极晶体管中的集电极到发射极穿通而被双极晶体管打开，或者通过由开关导通的双极晶体管进入正常导通耦合到双极晶体管的基极。在优选实施例中，开关是被设计成在固定阈值电压下经历源极到漏极击穿的MOS晶体管，于是它激活双极晶体管，该双极晶体管又导通过电压。以这种方式，可以获得大电流双极晶体管的优点，而不用担心制造变形会阻止双极晶体管提供所需的保护，例如仅依靠穿通现象的情况。

6. 发明授权

US5408147A VCC translator circuit 失效
标题翻译： VCC转换器电路
公开(公告)号：US5408147A
公开(公告)日：1995-04-18
申请号：US116920
申请日：1993-09-07
申请人： Roy L. Yarbrough , Jay R. Chapin
发明人： Roy L. Yarbrough , Jay R. Chapin
IPC分类号： H03K19/003 , H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/0013 , H03K19/018521 , H03K19/018592
摘要： A circuit for translating logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail in which the potentials of the two high-potential rails are not equal. The translator of the present invention is utilized in the transition from a 3V-supplied circuit to a 5V-supplied circuit, or vice versa, without any static current I.sub.CCt and regardless of the power-up sequencing. The static current is eliminated by isolating the output of the first stage of the translator, which is at the first high-potential power rail level, from all transistors of the second stage that are tied directly to the second high-potential power rail. In the preferred embodiment of the invention the transistors of the second stage that are powered by the second high-potential power rail are PMOS transistors and the isolation is achieved by linking those PMOS transistors to the first stage through a series of controlling NMOS transistors. In that way, the PMOS transistors will be completely turned off when necessary so as to avoid any undesirable conduction paths occurring due to differences in the potentials of the two high-potential power rails.
摘要翻译：用于将由一个高电位电源轨提供的电路的逻辑信号转换成由两个高电位轨道的电位不相等的另一个高电位电源轨提供的电路的电路。本发明的转换器用于从3V提供的电路到5V供电的电路的转换，反之亦然，而没有任何静态电流ICCt，而不管上电顺序如何。通过将直接连接到第二高电位电力轨的第二级的所有晶体管与位于第一高电位电力轨电平的转换器的第一级的输出隔离来消除静态电流。在本发明的优选实施例中，由第二高电位电源轨供电的第二级的晶体管是PMOS晶体管，并且通过一系列控制NMOS晶体管将那些PMOS晶体管连接到第一级来实现隔离。以这种方式，PMOS晶体管在必要时将完全关闭，以避免由于两个高电位电源轨的电位差而产生的任何不期望的导通路径。

7. 发明授权

US5289056A BICMOS input buffer circuit with integral passgate 失效
标题翻译：带集成通道的BICMOS输入缓冲电路
公开(公告)号：US5289056A
公开(公告)日：1994-02-22
申请号：US898029
申请日：1992-06-12
申请人： Susan M. Keown , Roy L. Yarbrough
发明人： Susan M. Keown , Roy L. Yarbrough
IPC分类号： H03K19/013 , H03K19/082 , H03K17/04
CPC分类号： H03K19/013 , H03K19/0826
摘要： A BICMOS input buffer circuit (20) incorporates an integral CMOS passgate circuit (P2,N2) between bipolar input (Q1) and output (Q3,Q4,Q5) transistors of the input buffer circuit. Latch enable inputs (LE) receive latch enable signals for operating the input buffer circuit and internal passgate in a transparent mode for passing data signals from the input (V.sub.IN) to the output (V.sub.OUT) and in a blocking mode for blocking data signals. The internal CMOS passgate circuit (P2,N2) is coupled into the input buffer circuit (20) to control nodes of the transistor output pullup (Q4,Q5) and pulldown (Q3) for controlling the conducting states of the respective transistor output pullup and pulldown to implement the blocking and transparent modes. A third passgate transistor (P3) may also be coupled between a control node (m1) of the transistor output pullup (Q4,Q5) and the low potential power rail (GND) for positive turn off of the output pullup. A dynamic power enhancement circuit (DPC) provides transient enhancement for the transition from the blocking mode to transparent mode.
摘要翻译： BICMOS输入缓冲电路（20）在输入缓冲电路的双极性输入（Q1）和输出（Q3，Q4，Q5）晶体管之间并入集成的CMOS通道电路（P2，N2）。锁存使能输入（LE）接收锁存使能信号，用于在透明模式下操作输入缓冲电路和内部通道，以将数据信号从输入（VIN）传送到输出（VOUT），并以阻塞模式阻塞数据信号。内部CMOS通路电路（P2，N2）耦合到输入缓冲电路（20）中以控制晶体管输出上拉（Q4，Q5）和下拉（Q3）的节点，用于控制各个晶体管输出上拉的导通状态，下拉以实现阻塞和透明模式。第三通道晶体管（P3）还可以耦合在晶体管输出上拉（Q4，Q5）的控制节点（m1）和低电位电源轨（GND）之间，用于输出上拉的正断开。动态功率增强电路（DPC）为从阻塞模式到透明模式的转换提供瞬态增强。

8. 发明授权

US5204554A Partial isolation of power rails for output buffer circuits 失效
标题翻译：用于输出缓冲电路的电源轨的部分隔离
公开(公告)号：US5204554A
公开(公告)日：1993-04-20
申请号：US802747
申请日：1991-12-06
申请人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , E. David Haacke , Roy L. Yarbrough
IPC分类号： H01L23/50 , H01L21/822 , H01L27/04 , H03K17/16 , H03K19/00 , H03K19/003
CPC分类号： H03K19/00346 , H03K17/16 , H01L2224/48091 , H01L2224/49175 , H01L2924/1305 , H01L2924/3011
摘要： An output buffer circuit (10) delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). The output buffer circuit comprises an input stage (12) coupled between a relatively quiet power supply rail (V.sub.CCQ) and a relatively quiet power ground rail (GNDQ), and an output stage (14) coupled between a relatively noisy power supply rail (V.sub.CCN) and a relatively noisy power ground rail (GNDN). A first coupling resistor (R5) is coupled between the relatively quiet and noisy supply rails (V.sub.CCQ, V.sub.CCN) for reducing V.sub.CC droop in the relatively noisy supply rail (V.sub.CCN) which in turn reduces output step in voltage during transition from low to high potential level (LH) at the output (V.sub.OUT). A second coupling resistor (R5A) is coupled between the relatively quiet and noisy ground rails (GNDQ,GNDN). The coupling resistors (R5 and R5A) have low resistance values selected for partially coupling the supply and ground rails respectively, while maintaining partial isolation for protecting input dynamic threshold levels of quiet outputs. The first coupling resistor (R5) is coupled between supply rail bond pads (20,22), while the second coupling resistor (R5A) is coupled between ground rail bond pads (30,32). The power rail bond pads (20,22) (30,32) are coupled respectively to split leads (24,25) (34,35) of a split lead leadframe merging respectively to a common V.sub.CC pin (28) and a common GND pin (38).

9. 发明授权

US5184034A State-dependent discharge path circuit 失效
标题翻译：状态依赖放电路径电路
公开(公告)号：US5184034A
公开(公告)日：1993-02-02
申请号：US804906
申请日：1991-12-06
申请人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
发明人： James R. Ohannes , Stephen W. Clukey , Ernest D. Haacke , Roy L. Yarbrough
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/08 , H03K19/082 , H03K19/088 , H03K19/0944
CPC分类号： H03K19/0826 , H03K19/00307 , H03K19/09448
摘要： A circuit for use in connection with tristate output buffers in order to provide concurrently for fast discharge of the output pulldown transistor base and at the same time for building in protection against reverse breakdown in the pulldown transistor. The innovation consists of providing a two discharge paths to ground for the base of the output pullup transistor. A low-capacitance path is activated only while the output buffer is in its active mode. In the preferred embodiment of the invention, this low discharge path consists of two CMOS transistors in series, one of which is controlled by the enable signal input E of the buffer circuit and the other by the data signal input V.sub.IN of the buffer circuit. The other path to ground is available whenever the data signal input V.sub.IN is low, regardless of whether the buffer is in its active or inactive mode. This other path provides discharge protection for the base of the pullup transistor for the buffer in its inactive mode, and has incorporated into it reverse breakdown protection in the form of voltage drop devices such as forward-biased diodes.

10. 发明授权

US07893566B2 Power latch 有权
标题翻译：电源锁定
公开(公告)号：US07893566B2
公开(公告)日：2011-02-22
申请号：US12403490
申请日：2009-03-13
申请人： Roy L. Yarbrough , Julie Stultz , Steven M. Macaluso
发明人： Roy L. Yarbrough , Julie Stultz , Steven M. Macaluso
IPC分类号： H02J1/00
CPC分类号： H03K3/356 , Y10T307/615 , Y10T307/696 , Y10T307/76 , Y10T307/858
摘要： A circuit that automatically, seamlessly connects the higher (or the lower) of two power supplies to an output is described. The circuit does not incur a one diode drop when the two power supplies are at about the same voltage levels, and the unused power supply draws no stand-by current. Cross coupled transistor and cross coupled inverters are employed.
摘要翻译：描述了自动地将两个电源的较高（或更低）连接到输出的电路。当两个电源处于大致相同的电压电平时，该电路不会产生一个二极管降压，而未使用的电源不会产生待机电流。采用交叉耦合晶体管和交叉耦合的反相器。

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