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1. 发明授权

US4999520A High speed TTL buffer circuit which is resistive to the influence of alpha-rays 失效
标题翻译：高速TTL缓冲电路，可抵抗α射线的影响
公开(公告)号：US4999520A
公开(公告)日：1991-03-12
申请号：US330461
申请日：1989-03-30
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K3/2885 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K19/086
摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.
摘要翻译：一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通的相分离电路。

2. 发明授权

US5298802A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
标题翻译：具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件
公开(公告)号：US5298802A
公开(公告)日：1994-03-29
申请号：US56798
申请日：1993-05-03
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.
摘要翻译：根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。射极跟随器输出电路由相位分离电路的反相输出驱动。同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动电路。作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

3. 发明授权

US5283480A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
公开(公告)号：US5283480A
公开(公告)日：1994-02-01
申请号：US557109
申请日：1990-07-25
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

4. 发明授权

US5126597A High speed IC device empolying non-threshold logic circuits to provide logic gates having different power and load requirements 失效
标题翻译：高速IC器件使非阈值逻辑电路能够提供具有不同功率和负载要求的逻辑门
公开(公告)号：US5126597A
公开(公告)日：1992-06-30
申请号：US548835
申请日：1990-07-06
申请人： Mitsuo Usami , Noboru Shiozawa , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Kaoru Koyu
IPC分类号： H03K19/00 , H03K19/013 , H03K19/018 , H03K19/086
CPC分类号： H03K19/0136 , H03K19/001 , H03K19/086
摘要： A unitary semiconductor integrated circuit is constructed using a non-threshold logic NTL circuit for a circuit which has a light load or a light load driving capability, using an NTL circuit additionally provided with an emitter-follower output circuit for effecting a circuit having a comparatively heavy load, and using a super pull-down logic (SPL) circuit for effecting a circuit having a heavy load. The NTL circuit thereof which receives an output signal generated by the emitter-follower output circuit or from the SPL circuit associated with a preceding logic gate circuit stage uses, as its operating voltage, the operating voltage of the emitter-follower output circuit or that of the SPL circuit.
摘要翻译：使用具有轻负载或轻负载驱动能力的电路的非阈值逻辑NTL电路构造单一半导体集成电路，使用另外设置有发射极跟随器输出电路的NTL电路，用于实现具有比较并且使用超级下拉逻辑（SPL）电路来实现具有重负载的电路。其接收由发射极跟随器输出电路产生的输出信号或与前一逻辑门电路级相关的SPL电路的输出信号的NTL电路使用射极跟随器输出电路的工作电压作为其工作电压 SPL电路。

5. 发明授权

US5910010A Semiconductor integrated circuit device, and process and apparatus for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法和装置
公开(公告)号：US5910010A
公开(公告)日：1999-06-08
申请号：US732215
申请日：1997-02-18
申请人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
发明人： Hirotaka Nishizawa , Tomoyoshi Miura , Ichirou Anjou , Masamichi Ishihara , Masahiro Yamamura , Sadao Morita , Takashi Araki , Kiyoshi Inoue , Toshio Sugano , Tetsuji Kohara , Toshio Yamada , Yasushi Sekine , Yoshiaki Anata , Masakatsu Goto , Norihiko Kasai , Shinobu Takeura , Mutsuo Tsukuda , Yasunori Yamaguchi , Jiro Sawada , Hidetoshi Iwai , Seiichiro Tsukui , Tadao Kaji , Noboru Shiozawa
IPC分类号： H01L21/56 , H01L21/98 , H01L23/495 , H01L25/065 , H01L21/52 , H01L21/58 , H01L21/60
CPC分类号： H01L24/06 , H01L21/565 , H01L23/4951 , H01L23/49575 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2225/06527 , H01L2225/06551 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01055 , H01L2924/01058 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/351
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.
摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部每一帧。然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。然后将树脂包装从模具部件中释放出来。

6. 发明授权

US09297722B2 Driver'S aid device and driver'S aid system 有权
标题翻译：司机助理装置及驾驶员辅助系统
公开(公告)号：US09297722B2
公开(公告)日：2016-03-29
申请号：US13386126
申请日：2010-07-16
申请人： Narumi Oguchi , Yasumasa Narumi , Youichi Tohyama , Akihiro Ishiduka , Noboru Shiozawa
发明人： Narumi Oguchi , Yasumasa Narumi , Youichi Tohyama , Akihiro Ishiduka , Noboru Shiozawa
IPC分类号： G08G1/123 , G01M17/007
CPC分类号： G01M17/0074
摘要： [Object] Object of the present invention is to improve accuracy of the travelling test of a tested vehicle on a chassis dynamometer, and to increase realistic feeling of the travelling test.[Means to solve] A driver's aid device 5 displays, on a main screen 11, a travelling speed pattern 12 that is a driving pattern for performing a performance evaluation test of a tested vehicle 6. The main screen 11 displays thereon topographical feature information 13 of a road where the travelling test is carried out. A marker 14 that indicates a vehicle state is shown at an intersection of the topographical feature information 13 and a reference line 15 that indicates a present position of the tested vehicle 6. This marker 14 is shown with the marker 14 inclined in accordance with a gradient of the road where the test is carried out. Further, a curve band 28 indicating curve information of the road where the travelling test is carried out is shown on the main screen 11. The curve band 28 is shown with a color of the curve band 28 changed in accordance with an angle of the curve. In addition, the travelling speed pattern 12 is created on the basis of data of GPS or a map data 10. Furthermore, a travelling route where the travelling test is carried out is displayed on an auxiliary display device on the basis of data to create the travelling speed pattern.
摘要翻译：本发明的目的在于提高测试车辆在底盘测功机上的行驶试验的精度，并提高行驶试验的现实感。 [解决方案]驾驶员辅助装置5在主画面11上显示作为用于进行被测试车辆6的性能评价试验的驾驶模式的行驶速度模式12.主画面11在其上显示地形特征信息13 在进行旅行测试的道路上。表示车辆状态的标记14被显示在表征特征信息13和表示被测试车辆6的当前位置的参考线15的交点处。该标记14被示出为具有根据梯度倾斜的标记14 在进行测试的道路上。此外，在主画面11上示出了表示进行行驶试验的道路的曲线信息的曲线带28。曲线带28被示出，曲线带28的颜色根据曲线的角度而变化。另外，基于GPS或地图数据10的数据来生成行驶速度模式12.此外，基于数据，在辅助显示装置上显示执行行驶测试的行驶路线，以创建行驶速度模式

7. 发明申请

US20120242513A1 DRIVER'S AID DEVICE AND DRIVER'S AID SYSTEM 有权
标题翻译：司机助手及司机助理系统
公开(公告)号：US20120242513A1
公开(公告)日：2012-09-27
申请号：US13386126
申请日：2010-07-16
申请人： Narumi Oguchi , Yasumasa Narumi , Youichi Tohyama , Akihiro Ishiduka , Noboru Shiozawa
发明人： Narumi Oguchi , Yasumasa Narumi , Youichi Tohyama , Akihiro Ishiduka , Noboru Shiozawa
IPC分类号： G08G1/133
CPC分类号： G01M17/0074
摘要： [Object] Object of the present invention is to improve accuracy of the travelling test of a tested vehicle on a chassis dynamometer, and to increase realistic feeling of the travelling test.[Means to solve] A driver's aid device 5 displays, on a main screen 11, a travelling speed pattern 12 that is a driving pattern for performing a performance evaluation test of a tested vehicle 6. The main screen 11 displays thereon topographical feature information 13 of a road where the travelling test is carried out. A marker 14 that indicates a vehicle state is shown at an intersection of the topographical feature information 13 and a reference line 15 that indicates a present position of the tested vehicle 6. This marker 14 is shown with the marker 14 inclined in accordance with a gradient of the road where the test is carried out. Further, a curve band 28 indicating curve information of the road where the travelling test is carried out is shown on the main screen 11. The curve band 28 is shown with a color of the curve band 28 changed in accordance with an angle of the curve. In addition, the travelling speed pattern 12 is created on the basis of data of GPS or a map data 10. Furthermore, a travelling route where the travelling test is carried out is displayed on an auxiliary display device on the basis of data to create the travelling speed pattern.
摘要翻译：本发明的目的在于提高测试车辆在底盘测功机上的行驶试验的精度，并提高行驶试验的现实感。 [解决方案]驾驶员辅助装置5在主画面11上显示作为用于进行被测试车辆6的性能评价试验的驾驶模式的行驶速度模式12.主画面11在其上显示地形特征信息13 在进行旅行测试的道路上。表示车辆状态的标记14被显示在表征特征信息13和表示被测试车辆6的当前位置的参考线15的交点处。该标记14被示出为具有根据梯度倾斜的标记14 在进行测试的道路上。此外，在主画面11上示出了表示进行行驶试验的道路的曲线信息的曲线带28。曲线带28被示出，曲线带28的颜色根据曲线的角度而变化。另外，基于GPS或地图数据10的数据来生成行驶速度模式12.此外，基于数据，在辅助显示装置上显示执行行驶测试的行驶路线，以创建行驶速度模式

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