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1. 发明授权

US5448195A Semiconductor integrated delay circuit 失效
标题翻译：半导体集成延迟电路
公开(公告)号：US5448195A
公开(公告)日：1995-09-05
申请号：US79758
申请日：1993-06-22
申请人： Tetsuya Iga , Koichi Hasegawa
发明人： Tetsuya Iga , Koichi Hasegawa
IPC分类号： H03K5/13
CPC分类号： H03K5/133
摘要： A semiconductor integrated circuit having a plurality of power source voltages in one chip and which comprises delaying means which accurately implements a predetermined delay time into a signal. An inverter circuit block receives at its input part an output from a NAND gate. An output from the inverter circuit block is coupled to a node of a phase comparing part through a switch. The output from the inverter circuit block is also coupled through another switch to an input part of another inverter circuit block whose output is coupled to the node of the phase comparing part through still another switch. A control signal is set at a L level if the phase comparing part is to operate at a first power source voltage and set at a H level if the phase comparing part is to operate at a second power source voltage which is larger than the first power source voltage.
摘要翻译：一种半导体集成电路，其具有一个芯片中的多个电源电压，并且包括将信号精确地实现预定的延迟时间的延迟装置。逆变器电路块在其输入部分接收来自“与非”门的输出。来自逆变器电路块的输出通过开关耦合到相位比较部分的节点。来自逆变器电路块的输出还通过另一个开关耦合到另一个反相器电路块的输入部分，其输出通过另一个开关耦合到相位比较部分的节点。如果相位比较部分工作在第一电源电压并且如果相位比较部分要在大于第一电源的第二电源电压下工作，则将控制信号设置为L电平源电压。

2. 发明授权

US5359241A ECL circuit 失效
标题翻译： ECL电路
公开(公告)号：US5359241A
公开(公告)日：1994-10-25
申请号：US54192
申请日：1993-04-30
申请人： Koichi Hasegawa , Tetsuya Iga
发明人： Koichi Hasegawa , Tetsuya Iga
IPC分类号： H03K3/286 , H03K3/012 , H03K3/2885 , H03K19/086 , H03K19/0175
CPC分类号： H03K3/2885 , H03K3/012
摘要： A flip-flop circuit of ECL structure includes an ECL circuit portion and a level shift circuit portion including a circuit having a pair of resistors. The ECL circuit portion applies a differential signal to one end of each of the resistors, and Q and/Q output signals are derived from the other ends of each of the resistors. The amount of level shift down of the signals when shifted by the resistors is enabled to be set to any relatively small amount, whereby the ECL circuit is permitted to operate at a low voltage.
摘要翻译： ECL结构的触发器电路包括ECL电路部分和包括具有一对电阻器的电路的电平移位电路部分。 ECL电路部分将差分信号施加到每个电阻器的一端，并且从每个电阻器的另一端导出Q和/ Q输出信号。当由电阻器移位时信号的电平偏移量能够被设置为任何相对较小的量，由此ECL电路被允许在低电压下操作。

3. 发明授权

US5581214A Phase-locked loop circuit 失效
标题翻译：锁相环电路
公开(公告)号：US5581214A
公开(公告)日：1996-12-03
申请号：US521587
申请日：1995-08-30
申请人： Tetsuya Iga
发明人： Tetsuya Iga
IPC分类号： H03L7/197 , H03K23/66 , H03L7/089 , H03L7/14 , H03L7/18 , H03L7/193 , H03L7/199 , H03L3/00 , H03L7/10 , H03L7/16
CPC分类号： H03L7/199 , H03K23/667 , H03L7/14 , H03L7/193 , H03L2207/08 , H03L7/0891
摘要： A timing generating circuit (9) receives a reference signal (f.sub.REF) and an operation control signal (S.sub.0) as inputs and outputs a generation control signal (S.sub.1). The generation control signal (S.sub.1) is inputted to the prescaler (31), the programmable divider (41) and a phase comparator (51). The generation control signal (S.sub.1) goes "H" when the operation control signal (S.sub.0) goes "H" and then the reference signal (f.sub.REF) is counted predetermined times, and a raw signal (f.sub.RAW) is divided to start generating a signal to be measured (f.sub.0) after the generation control signal (S.sub.1) goes "H", so that a phase difference .delta. between the reference signal (f.sub.REF) and the signal to be measured (f.sub.0) at the start is constant irrespective of the timing of the operation control signal (S.sub.0) attaining "H". Accordingly, it is not necessary to set the timing of the operation control signal (S.sub.0) attaining "H" considerably earlier prior to a period required in the time-division telegraphy, and the power consumption of a prescaler (31) and a programmable divider (41) are suppressed.
摘要翻译：定时发生电路（9）接收参考信号（fREF）和操作控制信号（S0）作为输入，并输出生成控制信号（S1）。生成控制信号（S1）输入到预分频器（31），可编程分频器（41）和相位比较器（51）。当操作控制信号（S0）变为“H”，然后对预定次数对参考信号（fREF）进行计数时，生成控制信号（S1）变为“H”，原始信号（fRAW）被分割开始产生信号在生成控制信号（S1）变为“H”之后被测量（f0），使得在开始时参考信号（fREF）和待测量信号（f0）之间的相位差增量是恒定的，而不管定时的操作控制信号（S0）达到“H”。因此，不需要在时分电报所需的时间之前将操作控制信号（S0）达到“H”的时间设定得较早，并且预分频器（31）和可编程分频器（41）被抑制。

4. 发明授权

US5459755A PLL circuit 失效
标题翻译： PLL电路
公开(公告)号：US5459755A
公开(公告)日：1995-10-17
申请号：US248181
申请日：1994-05-24
申请人： Tetsuya Iga , Naoyuki Kato
发明人： Tetsuya Iga , Naoyuki Kato
IPC分类号： H03L7/089 , H03L7/093 , H03L7/10 , H03L7/107 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0898 , H03L7/10
摘要： There is disclosed a PLL circuit wherein a delay circuit (3') of a phase comparator (30') receives a supply current (IC) from a first variable current source (.PHI.IC) and changes a delay time (.DELTA.T) in negative correlation with the amount of the supply current (IC), and the first variable current source (.PHI.IC) changes the amount of the supply current (IC) to the delay circuit (3') in accordance with the indication of a control signal (C1) serving as a supply current control signal for a second variable current source (.PHI.IA) and a third variable current source (.PHI.IB) of a charge pump circuit (31). Changes in delay time of the delay device of the phase comparing device are adapted such that the delay time is constantly suitable as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.
摘要翻译：公开了一种PLL电路，其中相位比较器（30'）的延迟电路（3'）从第一可变电流源（PHI IC）接收电源电流（IC），并将延迟时间（DELTA T）改变为负与电源电流（IC）的量的相关性，并且第一可变电流源（PHI IC）根据控制信号的指示将延迟电路（3'）的供给电流（IC）的量改变 C1）用作电荷泵电路（31）的第二可变电流源（PHI IA）和第三可变电流源（PHI IB）的电源电流控制信号。调整相位比较装置的延迟装置的延迟时间的变化，使得随着充电泵电路的相位比较电压信号的电流量的变化，延迟时间是不断适合的，从而可以减少锁定时间。

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