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1. 发明申请

US20040262785A1 Terminal structure of multi-layer substrate and method for forming the same 审中-公开
标题翻译：多层基板的端子结构及其形成方法
公开(公告)号：US20040262785A1
公开(公告)日：2004-12-30
申请号：US10791718
申请日：2004-03-04
发明人： Seok Taek Jun
IPC分类号： H01L029/40
CPC分类号： H05K3/3442 , H01L23/13 , H01L23/49805 , H01L23/49827 , H01L23/49833 , H01L2224/48227 , H01L2924/09701 , H05K2201/09172 , H05K2201/10727 , Y02P70/613
摘要： Disclosed is a terminal structure of a multi-layer substrate and a method for forming the same. In the terminal structure, a plurality of terminals are formed on at least two adjacent substrate layers, each of the terminals being spaced from adjacent ones to a predetermined interval. Openings are formed in at least one of the substrate layers. Each of the openings is formed between each adjacent ones of first terminals in the at least one substrate layer, and spaced from the each first terminals to a predetermined gap, and has a size same as that of the first terminals. The substrate layers are stacked one atop another and compressed together so that second terminals formed on at least one corresponding substrate layer are projected to a plane of an outermost substrate layer on which corresponding terminals are formed. The terminal structure and the method can secure a predetermined interval to a plurality of terminals in a package when the terminals are formed as well as simplify formation thereof.
摘要翻译：公开了多层基板的端子结构及其形成方法。在端子结构中，在至少两个相邻的基板层上形成多个端子，每个端子与相邻的基板间隔开至预定间隔。开口形成在至少一个基板层中。每个开口形成在至少一个基板层中的每个相邻的第一端子之间，并且与每个第一端子间隔开至预定的间隙，并且具有与第一端子的尺寸相同的尺寸。将基板层叠在一起并压缩在一起，使形成在至少一个对应基板层上的第二端子突出到形成相应端子的最外层基板层的平面上。当端子形成时，端子结构和方法可以确保封装中的多个端子的预定间隔，并且简化其形成。

2. 发明申请

US20040262777A1 Components, methods and assemblies for multi-chip packages 有权
标题翻译：用于多芯片封装的组件，方法和组件
公开(公告)号：US20040262777A1
公开(公告)日：2004-12-30
申请号：US10683097
申请日：2003-10-10
申请人： Tessera, Inc.
发明人： Young-Gon Kim , David Gibson , Michael Warner , Philip Damberg , Philip Osborn
IPC分类号： H01L023/48 , H01L029/40 , H05K007/02
CPC分类号： H05K1/141 , H01L25/105 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/3511 , H05K3/3436 , H05K2201/10719 , H05K2203/1572 , H01L2924/00 , H01L2224/05644 , H01L2924/00014 , H01L2224/05647
摘要： An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.
摘要翻译：具有独立测试和修复功能的超薄系统级封装（SIP）包括：插入器，其布置在其顶表面和底表面上，多个封装的半导体芯片通过焊料凸块安装，根据Land Grid Array （LGA）格式，并且其中在SIP上不使用底部填充物。

3. 发明申请

US20040262757A1 Semiconductor device, ball grid array connection system, and method of making 有权
标题翻译：半导体器件，球栅阵列连接系统及制作方法
公开(公告)号：US20040262757A1
公开(公告)日：2004-12-30
申请号：US10890184
申请日：2004-07-14
发明人： Larry D. Kinsman , Salman Akram
IPC分类号： H01L021/48 , H01L029/40
CPC分类号： H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/49109 , H01L2224/73215 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having at least one conductor thereon. A top insulating layer of the multilayer structure contains a ball grid array. The metal layer is used as an electrical ground plane to simplify the routing pattern of conductive traces on the insulating material. The metal layer may also be used to dissipate heat from the die. The conductors of the multilayer structure provide additional versatility in wiring the die to the ball grid array.

4. 发明申请

US20040245618A1 Integrated circuit and method for fabricating an integrated circuit 有权
标题翻译：用于制造集成电路的集成电路和方法
公开(公告)号：US20040245618A1
公开(公告)日：2004-12-09
申请号：US10831455
申请日：2004-04-23
申请人： Infineon Technologies AG
发明人： Albrecht Mayer
IPC分类号： H01L021/44 , H01H073/00 , H01L023/22 , H01L029/40
CPC分类号： H01L25/50 , G03F1/50 , G03F7/70466 , H01L25/0655 , H01L27/0203 , H01L2224/48227 , H01L2224/49171 , H01L2924/10253 , H01L2924/00
摘要： In an integrated circuit having a first circuit part and at least one second circuit part, which is assigned to a specific functionality of the first circuit part, on one and the same silicon wafer, of which the first circuit part and the at least one circuit part are arranged in non-overlapping, mutually separate regions of the silicon wafer and are connected to one another via connecting elements or lines, during the fabrication, for each exposure plane, with the exception of the exposure plane used for the fabrication of the connecting elements or lines, use is made in each case of a first exposure mask intended for the first circuit part and a second exposure mask intended for the second circuit part. These first and second exposure masks may be arranged on a common reticle for a respective exposure plane.
摘要翻译：在具有分配给第一电路部分的特定功能的第一电路部分和至少一个第二电路部分的集成电路中，在同一个硅晶片上，其中第一电路部分和至少一个电路部分布置在硅晶片的非重叠，相互分离的区域中，并且在制造期间通过连接元件或线彼此连接，对于每个曝光平面，除了用于制造连接的曝光平面在第一电路部分的第一曝光掩模和用于第二电路部分的第二曝光掩模的每种情况下都使用元件或线。这些第一和第二曝光掩模可以布置在相应的曝光平面的公共掩模版上。

5. 发明申请

US20040232512A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20040232512A1
公开(公告)日：2004-11-25
申请号：US10874363
申请日：2004-06-24
申请人： RENESAS TECHNOLOGY CORP.
发明人： Eiji Hasunuma , Hideki Genjo , Shigeru Shiratake , Atsushi Hachisuka , Koji Taniguchi
IPC分类号： H01L021/336 , H01L029/40
CPC分类号： H01L27/10852 , H01L21/28568 , H01L21/76814 , H01L21/76831 , H01L27/10808
摘要： In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.
摘要翻译：在半导体装置中，为了满足半导体装置的小型化使接触孔的直径减小的要求，没有被氢氟酸腐蚀的抗HF侧壁膜由隔离膜形成，例如氮化物膜设置在接触孔的侧壁上。此外，在接触孔下端附近的硅衬底1中设置有连接到一对n型源极/漏极区域中的一个和到达p型隔离区域的第一杂质区域的第二杂质区域。由于这种结构，可以根据小型半导体器件的需要防止用于形成互连层的直径的膨胀，因此可以提供稳定半导体器件的操作特性的半导体器件及其制造方法。

6. 发明申请

US20040222520A1 INTEGRATED CIRCUIT PACKAGE WITH FLAT METAL BUMP AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：具有平面金属保护的集成电路封装及其制造方法
公开(公告)号：US20040222520A1
公开(公告)日：2004-11-11
申请号：US10251512
申请日：2002-09-19
发明人： Yonggang Jin
IPC分类号： H01L021/44 , H01L021/48 , H01L021/50 , H01L029/40
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/05001 , H01L2224/05022 , H01L2224/05184 , H01L2224/05572 , H01L2224/1147 , H01L2224/13099 , H01L2224/13144 , H01L2924/0001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/00014 , H01L2224/05644 , H01L2224/05124 , H01L2224/05166 , H01L2224/05171
摘要： A flat gold bump, and manufacturing method therefor, is provided. An under bump metallurgy is formed on the contact pad in and around the opening. A bump pad is formed over the under bump metallurgy and a flat gold bump is formed on and over the bump pad.
摘要翻译：提供平坦的金凸块及其制造方法。在开口内部和周围的接触垫上形成凸块下冶金。在凸块下方形成凸块，并在凸块上形成平坦的金凸点。

7. 发明申请

US20040212073A1 DC-DC converter implemented in a land grid array package 有权
标题翻译： DC-DC转换器实现在一个平面阵列封装中
公开(公告)号：US20040212073A1
公开(公告)日：2004-10-28
申请号：US10423603
申请日：2003-04-24
申请人： POWER-ONE LIMITED
发明人： Mysore Purushotham Divakar , David Keating , Antoin Russell
IPC分类号： H01L023/48 , H01L029/40
CPC分类号： H02M3/00 , H01L23/3677 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/45099 , H01L2224/48227 , H01L2224/48471 , H01L2224/49111 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H02M3/1588 , Y02B70/1466 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip package that includes a DC-DC converter implemented with a land grid array for interconnection and surface mounting to a printed circuit board. The package includes a two layer substrate comprising a top surface and a bottom surface. At least one via array extends through the substrate. Each via in a via array includes a first end that is proximate to the top surface of the substrate and a second end that is proximate to the bottom surface of the substrate. At least one die attach pad is mounted on the top surface of the substrate and is electrically and thermally coupled to the via array. The DC-DC converter includes at least one power semiconductor die having a bottom surface that forms an electrode. The power semiconductor die is mounted on a die attach pad such that the bottom surface of the die is in electrical contact with the die attach pad. The bottom of the package forms a land grid array. The land grid array includes external pads that are separated into an interior region and a peripheral region. Each external pad located in the interior region of the land grid array is electrically and thermally coupled a via array.
摘要翻译：一种半导体芯片封装，其包括用陆架网格阵列实现的用于互连和表面安装到印刷电路板的DC-DC转换器。该包装包括包括顶表面和底表面的双层基底。至少一个通孔阵列延伸穿过基底。通孔阵列中的每个通孔包括靠近基板的顶表面的第一端和靠近基板的底表面的第二端。至少一个管芯附着垫安装在衬底的顶表面上并且电连接和热耦合到通孔阵列。 DC-DC转换器包括具有形成电极的底表面的至少一个功率半导体管芯。功率半导体管芯安装在管芯附接垫上，使得管芯的底表面与管芯附接垫电接触。封装的底部形成一个焊盘网格阵列。地面栅格阵列包括分离成内部区域和外围区域的外部焊盘。位于焊盘栅格阵列的内部区域中的每个外部焊盘电气和热耦合通孔阵列。

8. 发明申请

US20040207090A1 Low capacitance wiring layout and method for making same 失效
公开(公告)号：US20040207090A1
公开(公告)日：2004-10-21
申请号：US10842455
申请日：2004-05-11
发明人： Paul A. Farrar
IPC分类号： H01R012/04 , H05K001/11 , H01L023/48 , H01L023/52 , H01L029/40
CPC分类号： H01L23/522 , H01L23/5222 , H01L23/528 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

9. 发明申请

US20040201111A1 Interposer substrates with multisegment interconnect slots, semiconductor die packages including same, semiconductor dice for use therewith and methods of fabrication 有权
标题翻译：具有多段互连槽的插入式衬底，包括其的半导体管芯封装，与其一起使用的半导体管芯和制造方法
公开(公告)号：US20040201111A1
公开(公告)日：2004-10-14
申请号：US10409804
申请日：2003-04-09
发明人： Blaine J. Thurgood
IPC分类号： H01L023/48 , H01L029/40 , H01L021/44
CPC分类号： H01L23/13 , H01L24/48 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/4824 , H01L2224/73215 , H01L2224/85399 , H01L2924/00014 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , Y10T428/24273 , Y10T428/24917 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads is accessed for electrical attachment, as by wire bonding, to conductive traces on the opposite side of the interposer substrate. One or more reinforcements in the form of crosspieces or bridges span and segment intermediate portions of the substrate slot to resist bending stresses acting in the slot region proximate the centerline of the interposer substrate tending to crack or delaminate a polymer wire bond mold cap filling and covering the slot and the wire bonds. Various interposer substrate configurations are also disclosed, as are methods of fabrication.
摘要翻译：板上芯片（BOC）半导体封装包括多段纵向狭缝插入器衬底，细长的管芯接合焊盘通过该基板访问用于通过引线接合电连接到插入器衬底的相对侧上的导电迹线。横梁或桥梁形式的一个或多个增强件横跨和分段基板狭槽的中间部分，以抵抗作用在插入件基板的中心线附近的槽区域中的弯曲应力，倾向于破裂或分层聚合物线接合模盖填充和覆盖插槽和引线键。还公开了各种内插衬底配置，制造方法也是如此。

10. 发明申请

US20040188845A1 Semiconductor device having multilayer interconnection structure and method for manufacturing the device 失效
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US20040188845A1
公开(公告)日：2004-09-30
申请号：US10805403
申请日：2004-03-22
申请人： NEC Electronics Corporation
发明人： Manabu Iguchi , Akira Matumoto , Masahiro Komuro
IPC分类号： H01L029/40
CPC分类号： H01L23/564 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.
摘要翻译：具有多层互连结构的半导体器件包括芯片半导体衬底，设置在芯片半导体衬底上的多个层间绝缘层，设置在芯片半导体衬底上的电路部分和延伸穿过层间绝缘层的多个壁，以及沿着芯片半导体衬底的周边部分布置，使得壁围绕电路部分。墙壁包括上部的下部墙壁和下部的下部墙壁。上侧壁延伸穿过层间绝缘层之一并进一步延伸到设置在上部底壁延伸的层下方的另一层间绝缘层中。下侧壁延伸穿过设置在上部下壁延伸的层下方的层间绝缘层之一。上部下壁的下部各自延伸到下部副壁的对应的上部。

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