专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20040188845A1 Semiconductor device having multilayer interconnection structure and method for manufacturing the device 失效
标题翻译：具有多层互连结构的半导体器件及其制造方法
公开(公告)号：US20040188845A1
公开(公告)日：2004-09-30
申请号：US10805403
申请日：2004-03-22
申请人： NEC Electronics Corporation
发明人： Manabu Iguchi , Akira Matumoto , Masahiro Komuro
IPC分类号： H01L029/40
CPC分类号： H01L23/564 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a multilayer interconnection structure includes a chip semiconductor substrate, a plurality of interlayer insulating layers disposed on the chip semiconductor substrate, a circuit section disposed on the chip semiconductor substrate, and a plurality of walls that extend through the interlayer insulating layers and are arranged along the peripheral portions of the chip semiconductor substrate such that the walls surround the circuit section. The walls include upper sub-walls and lower sub-walls. The upper sub-walls extend through one of the interlayer insulating layers and further extend into another one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. The lower sub-walls extend through one of the interlayer insulating layers disposed under the layer through which the upper sub-walls extend. Lower portions of the upper sub-walls each extend into corresponding upper portions of the lower sub-walls.
摘要翻译：具有多层互连结构的半导体器件包括芯片半导体衬底，设置在芯片半导体衬底上的多个层间绝缘层，设置在芯片半导体衬底上的电路部分和延伸穿过层间绝缘层的多个壁，以及沿着芯片半导体衬底的周边部分布置，使得壁围绕电路部分。墙壁包括上部的下部墙壁和下部的下部墙壁。上侧壁延伸穿过层间绝缘层之一并进一步延伸到设置在上部底壁延伸的层下方的另一层间绝缘层中。下侧壁延伸穿过设置在上部下壁延伸的层下方的层间绝缘层之一。上部下壁的下部各自延伸到下部副壁的对应的上部。

2. 发明申请

US20040150073A1 Semiconductor device having superior resistance to moisture 失效
标题翻译：具有优异的抗潮湿性的半导体装置
公开(公告)号：US20040150073A1
公开(公告)日：2004-08-05
申请号：US10753326
申请日：2004-01-09
申请人： NEC ELECTRONICS CORPORATION
发明人： Akira Matumoto , Tadashi Fukase , Manabu Iguchi , Masahiro Komuro
IPC分类号： H01L023/58 , H01L023/02
CPC分类号： H01L23/564 , H01L23/28 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.
摘要翻译：在半导体器件中，电路单元形成在内部，并且围绕周边形成围绕由金属层的壁构成的内部的密封环。在拐角处，密封圈除了沿着周边延伸的直线部分之外还包括向内延伸的直线部分，由此密封环形成为在每个拐角处具有小矩形平面图案的平面图案。

3. 发明申请

US20030204832A1 Automatic generation method of dummy patterns 审中-公开
标题翻译：虚拟模式的自动生成方法
公开(公告)号：US20030204832A1
公开(公告)日：2003-10-30
申请号：US10423069
申请日：2003-04-25
申请人： NEC Electronics Corporation
发明人： Akira Matumoto
IPC分类号： G06F017/50 , G06F009/455
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： An automatic generation method of dummy patterns of the present invention includes: a first step of preparing a plurality of dummy pattern components which have regularly arranged dummy patterns, respectively, and for which priorities are set based upon a predetermined rule; a second step of selecting one of the plurality of dummy pattern components and arranging dummy patterns belonging to the selected dummy pattern component to overlap layout data of mask patterns for which arrangement prohibition regions are set; a third step of deleting dummy patterns which are in contact with or overlap the arrangement prohibition regions among the arranged dummy patterns; and a fourth step of deleting dummy patterns belonging to the dummy pattern component with a lower priority in the case in which a plurality of dummy patterns are in contact with or overlap each other.
摘要翻译：本发明的虚拟图案的自动生成方法包括：第一步骤，准备分别具有规则排列的虚拟图案的多个虚拟图案组件，并且基于预定规则设定优先级; 选择所述多个虚拟图案组分中的一个并且排列属于所选择的虚拟图案分量的虚拟图案以重叠设置了布置禁止区域的掩模图案的布局数据的第二步骤; 第三步骤，在布置的虚拟图案中删除与布置禁止区域接触或重叠的虚拟图案; 以及第四步骤，在多个虚设图案相互接触或重叠的情况下，以较低的优先级删除属于该虚拟图案组件的虚拟图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式