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1. 发明授权

US09978762B2 Semiconductor device and method of fabricating semiconductor device 有权
公开(公告)号：US09978762B2
公开(公告)日：2018-05-22
申请号：US15487419
申请日：2017-04-13
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Ching Hsu , Ko-Chi Chen , Shen-De Wang
IPC分类号： H01L27/11531 , H01L27/11529 , H01L27/11573
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11531 , H01L27/11536 , H01L27/11539 , H01L27/11573
摘要： A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

2. 发明授权

US09972493B2 Method of forming low height split gate memory cells 有权
公开(公告)号：US09972493B2
公开(公告)日：2018-05-15
申请号：US15594883
申请日：2017-05-15
申请人： Silicon Storage Technology, Inc.
发明人： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC分类号： H01L21/336 , H01L21/28 , H01L21/306 , G11C16/04 , H01L29/772 , H01L29/423
CPC分类号： H01L21/28 , G11C16/0425 , H01L21/28273 , H01L21/30604 , H01L27/11539 , H01L29/42328 , H01L29/772
摘要： A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

3. 发明申请

US20180061709A1 MARKED PIXEL UNIT, DISPLAY DEVICE USING THE SAME, AND METHOD FOR FABRICATING THE DISPLAY DEVICE 审中-公开
公开(公告)号：US20180061709A1
公开(公告)日：2018-03-01
申请号：US15646236
申请日：2017-07-11
申请人： AU OPTRONICS CORPORATION
发明人： Chia-Hui PAI , Wen-Hsien TSENG , Hsin-Ju WU , Yh-Hung LEE , You-Yuan HU , Teng-Yi WANG , Wei-Chieh CHEN , Kuan-Yi LEE , Kuan-Hsien WU , Chih-chun YANG
IPC分类号： H01L21/768 , H01L27/11539 , H01L27/12 , H01L27/146 , H01L23/50 , H01L29/417
CPC分类号： H01L21/76897 , H01L23/50 , H01L27/11539 , H01L27/124 , H01L27/1259 , H01L27/14621 , H01L29/41733
摘要： A marked pixel unit includes at least one active element, a first dielectric layer, a color filter unit, a second dielectric layer, and at least one pixel electrode. The active element includes a source, a gate, and a drain. The first dielectric layer is configured to cover the gate. The color filter unit is disposed above the first dielectric layer, and has an alignment opening. The second dielectric layer is disposed above the active element and the color filter unit, and has a contact hole. The pixel electrode is disposed above the second dielectric layer, and electrically connected to the drain through the contact hole. The contact hole of the second dielectric layer is located outside the alignment opening.

4. 发明申请

US20180053773A1 INTEGRATION OF FLOATING GATE MEMORY AND LOGIC DEVICE IN REPLACEMENT GATE FLOW 有权
公开(公告)号：US20180053773A1
公开(公告)日：2018-02-22
申请号：US15241759
申请日：2016-08-19
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L27/115 , H01L29/51 , H01L29/788 , H01L29/78
CPC分类号： H01L27/11539 , H01L21/28273 , H01L27/11536 , H01L29/513 , H01L29/66825 , H01L29/785 , H01L29/7881 , H01L29/7883
摘要： After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

5. 发明申请

US20180040482A1 Method Of Forming Low Height Split Gate Memory Cells 有权
公开(公告)号：US20180040482A1
公开(公告)日：2018-02-08
申请号：US15594883
申请日：2017-05-15
申请人： Silicon Storage Technology, Inc.
发明人： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC分类号： H01L21/28 , H01L29/423 , H01L29/772 , H01L21/306 , G11C16/04
CPC分类号： H01L21/28 , G11C16/0425 , H01L21/28273 , H01L21/30604 , H01L27/11539 , H01L29/42328 , H01L29/772
摘要： A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.

6. 发明授权

US09583640B1 Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure 有权
标题翻译：包括形成非易失性存储单元的控制栅极和半导体结构的方法
公开(公告)号：US09583640B1
公开(公告)日：2017-02-28
申请号：US14982028
申请日：2015-12-29
申请人： GLOBALFOUNDRIES Inc.
发明人： Ralf Richter , Sven Beyer , Carsten Grass , Tom Herrmann
IPC分类号： H01L29/788 , H01L29/66 , H01L29/423 , H01L27/115
CPC分类号： H01L29/7887 , H01L27/11531 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543 , H01L29/42328 , H01L29/42332 , H01L29/665 , H01L29/66825 , H01L29/7881
摘要： A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.
摘要翻译：一种方法包括提供包括非易失性存储单元元件的半导体结构，所述非易失性存储单元元件包括在半导体材料上形成的浮置栅极，选择栅极和擦除栅极，所述选择栅极和擦除栅极被布置在所述浮置栅极的相对侧，控制栅极绝缘材料层，在所述控制栅极绝缘材料层上方形成控制栅极材料层，执行在所述浮动栅极上形成控制栅极的第一图案化工艺，并且包括第一蚀刻工艺，所述第一蚀刻工艺选择性地去除所述控制栅极材料层相对于所述控制栅极绝缘材料层的材料，并且执行对所述控制栅极绝缘材料层进行图案化的第二图案化工艺，所述图案化的控制栅极绝缘材料层覆盖所述半导体结构的不被控制门。

7. 发明授权

US09543312B1 Method for manufacturing a nonvolatile memory device 有权
标题翻译：非易失性存储器件的制造方法
公开(公告)号：US09543312B1
公开(公告)日：2017-01-10
申请号：US14943680
申请日：2015-11-17
申请人： SK hynix Inc.
发明人： Do-Young Kim
IPC分类号： H01L27/115 , H01L29/66 , H01L21/265 , H01L21/28 , H01L29/36 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11546 , H01L21/28273 , H01L21/823807 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L27/11543 , H01L29/105 , H01L29/66575
摘要： A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an NMOS region and a PMOS region; performing a well forming ion implantation over the substrate in the cell region and the NMOS region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the NMOS region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode may have P-type conductivity.
摘要翻译：根据本发明的实施例的非易失性存储器件的制造方法可以包括提供包括单元区域和周边区域的衬底，其中所述外围区域包括NMOS区域和PMOS区域; 在所述单元区域和所述NMOS区域中的所述衬底上执行阱形成离子注入; 在所述单元区域和所述NMOS区域中的所述衬底的表面上执行阈值电压调整离子注入; 在所述单元区域和所述周边区域中形成包括浮置栅电极的栅极图案; 以及在所述单元区域的表面上执行结离子注入，其中所述浮栅电极可具有P型导电性。

8. 发明授权

US09466373B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US09466373B2
公开(公告)日：2016-10-11
申请号：US14197628
申请日：2014-03-05
申请人： Kabushiki Kaisha Toshiba
发明人： Nobuaki Okada , Masayuki Akou , Mitsuhiro Noguchi
IPC分类号： G11C16/08 , G11C16/10 , G11C7/14 , G11C8/08 , G11C11/56 , G11C16/04 , H01L27/115
CPC分类号： G11C16/10 , G11C7/14 , G11C8/08 , G11C11/5621 , G11C16/0483 , G11C16/08 , G11C2211/5641 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541
摘要： According to one embodiment, a nonvolatile semiconductor storage device includes a word line transfer unit which transfers voltage applied to a memory cell selected on the basis of an address to a word line. The word line transfer unit includes a word line transfer transistor which is arranged in a first layout area of the word line transfer unit and transfers voltage applied to the memory cell to the word line and a dummy word line transfer transistor which is arranged in a second layout area provided outside an end of the first layout area and does not transfer voltage applied to the memory cell to the word line.
摘要翻译：根据一个实施例，非易失性半导体存储装置包括字线传送单元，该字线传送单元将施加到基于地址的存储单元的电压传送到字线。字线传送单元包括字线传输晶体管，该字线传输晶体管布置在字线传送单元的第一布局区域中，并将施加到存储单元的电压传送到字线;以及虚拟字线传输晶体管，布置区域设置在第一布局区域的一端之外，并且不将施加到存储器单元的电压传送到字线。

9. 发明申请

US20160293616A1 SEMICONDUCTOR TRANSISTOR AND FLASH MEMORY, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体晶体管和闪存存储器及其制造方法
公开(公告)号：US20160293616A1
公开(公告)日：2016-10-06
申请号：US14675754
申请日：2015-04-01
申请人： Powerchip Technology Corporation
发明人： Yukihiro Nagai
IPC分类号： H01L27/115 , H01L29/66 , H01L29/51 , H01L29/788 , H01L29/78
CPC分类号： H01L27/11526 , H01L21/2652 , H01L21/26586 , H01L27/11519 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L29/4925 , H01L29/4983 , H01L29/513 , H01L29/66492 , H01L29/6659 , H01L29/66825 , H01L29/7833 , H01L29/7836 , H01L29/788
摘要： A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties.
摘要翻译：设置在基板上的闪存。闪速存储器包括包括堆叠的栅极结构，轻掺杂区域和间隔物的半导体晶体管。堆叠的栅极结构包括顺序地设置在衬底上的栅介质层，第一导电层，电介质层和第二导电层。电介质层在其周围具有开口，使得第一导电层与第二导电层电连接。轻掺杂区域在堆叠栅极结构的侧面处的开口下方设置在基板中。间隔件设置在堆叠的门结构的侧壁上。通过控制开口下方的第一导电层的高度来调节间隔物的宽度。通过使用电介质层作为掩模层来设置轻掺杂区域，以便获得轻掺杂区域的边缘以获得良好的电性能。

10. 发明授权

US09231113B2 Flash memory with P-type floating gate 有权
标题翻译：带P型浮动门的闪存
公开(公告)号：US09231113B2
公开(公告)日：2016-01-05
申请号：US14531857
申请日：2014-11-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： Kenji Sato
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49
CPC分类号： H01L29/788 , H01L21/28114 , H01L21/28273 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L29/42324 , H01L29/42376 , H01L29/4916
摘要： Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.
摘要翻译：描述了用于制造包括具有减小和较小的可变栅极电阻的外围晶体管的非易失性存储器件的方法。在一些实施例中，NAND型闪速存储器可以包括浮栅晶体管和外围晶体管（或非浮栅晶体管）。外围晶体管可以包括位于存储器阵列区域外的选择栅极晶体管（例如，漏极侧选择栅极和/或源极选择栅极）和/或逻辑晶体管。浮栅晶体管可以包括第一导电类型（例如，n型）的浮置栅极和包括不同于第一导电类型（例如，p型）的第二导电类型的下部的控制栅极。外围晶体管可以包括包括第一导电类型的第一层，第二导电类型的第二层的栅极和包括延伸穿过第二层的一个或多个侧壁扩散阻挡层的切口区域和第一层的一部分。

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