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1. 发明授权

US07652378B2 Aluminum-based interconnection in bond pad layer 有权
标题翻译：接合垫层中的铝基互连
公开(公告)号：US07652378B2
公开(公告)日：2010-01-26
申请号：US11582129
申请日：2006-10-17
申请人： Horng-Huei Tseng , Chenming Hu
发明人： Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L23/53223 , H01L24/02 , H01L2224/04073 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025
摘要： A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.
摘要翻译：提供了一种有效利用芯片面积的半导体金属结构。该结构包括衬底，在衬底上的铜基互连结构，铜基互连结构包括通过通孔连接的多个金属化层和在第一介电层中的至少一个铝基层，并连接到铜的所述互连结构，其中所述至少一个铝基层的顶层包括接合焊盘和连接到两个底部通孔的互连线，连接铜基互连结构的顶层的通孔/触点和底层的至少一个铝基层，其中所述通孔/触点位于第二电介质层中，以及覆盖所述至少一个铝基层的第三电介质层，其中所述接合焊盘通过所述第三电介质中的开口暴露层。

2. 发明申请

US20080102198A1 BONDING STRUCTURE AND FABRICATION THEREOF 有权
标题翻译：粘结结构与制造
公开(公告)号：US20080102198A1
公开(公告)日：2008-05-01
申请号：US11964195
申请日：2007-12-26
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： B05D5/10
CPC分类号： H01L24/05 , H01L21/76849 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/5329 , H01L24/03 , H01L24/13 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05147 , H01L2224/05647 , H01L2224/05681 , H01L2224/05684 , H01L2224/13101 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48647 , H01L2224/48684 , H01L2224/48747 , H01L2224/48784 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48781 , H01L2224/48681
摘要： A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
摘要翻译：公开了一种接合结构及其制造方法。本发明的接合结构包括形成在绝缘体层中的铜基焊盘和基本上覆盖铜基焊盘顶表面的保护层。保护层是自对准的，其材料选自金属氮化物，铜合金，铜化合物及其组合。

3. 发明申请

US20070085209A1 Anchored damascene structures 有权
标题翻译：锚定镶嵌结构
公开(公告)号：US20070085209A1
公开(公告)日：2007-04-19
申请号：US11252498
申请日：2005-10-18
申请人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
发明人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps
摘要翻译：埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤

4. 发明申请

US20060234438A1 Self-aligned contact for silicon-on-insulator devices 审中-公开
标题翻译：绝缘体上硅器件的自对准接触
公开(公告)号：US20060234438A1
公开(公告)日：2006-10-19
申请号：US11454600
申请日：2006-06-16
申请人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
发明人： Fu-Liang Yang , Yee-Chia Yeo , Horng-Huei Tseng , Chenming Hu
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L2029/7858 , H01L2924/3011
摘要： A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.
摘要翻译：一种用于形成与超薄体晶体管的自对准接触的方法，其首先提供具有由栅极叠层操作的源极和漏极区域的超薄体晶体管; 在栅极堆叠上形成接触间隔物; 形成覆盖晶体管的钝化层; 在所述钝化层中形成暴露所述接触间隔物和所述源极/漏极区域的接触孔; 用导电材料填充接触孔; 并建立与源极/漏极区域的电连通。

5. 发明申请

US20060229683A1 Method and system for magnetic shielding in semiconductor integrated circuit 有权
公开(公告)号：US20060229683A1
公开(公告)日：2006-10-12
申请号：US11089969
申请日：2005-03-25
申请人： Chao-Hsiung Wang , Horng-Huei Tseng , Denny Tang , Wen-Chin Lin , Mark Hsieh
发明人： Chao-Hsiung Wang , Horng-Huei Tseng , Denny Tang , Wen-Chin Lin , Mark Hsieh
IPC分类号： A61N1/00
CPC分类号： G11C11/16 , G11C5/025 , H01L23/5225 , H01L27/222 , H01L43/12 , H01L2924/0002 , H01L2924/00
摘要： A circuit with an inter-module radiation interference shielding mechanism is disclosed. The circuit includes a circuit module producing a radiation field. At least one radiation shielding module is situated between the circuit module and another module that is vulnerable to the interference of the radiation field. The shielding module is substantially tangential to the radiation field.

6. 发明申请

US20050194683A1 Bonding structure and fabrication thereof 审中-公开
标题翻译：粘结结构及其制造
公开(公告)号：US20050194683A1
公开(公告)日：2005-09-08
申请号：US10795736
申请日：2004-03-08
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L21/76849 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/5329 , H01L24/03 , H01L24/13 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05147 , H01L2224/05647 , H01L2224/05681 , H01L2224/05684 , H01L2224/13101 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48647 , H01L2224/48684 , H01L2224/48747 , H01L2224/48784 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48781 , H01L2224/48681
摘要： A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
摘要翻译：公开了一种接合结构及其制造方法。本发明的接合结构包括形成在绝缘体层中的铜基焊盘和基本上覆盖铜基焊盘顶表面的保护层。保护层是自对准的，其材料选自金属氮化物，铜合金，铜化合物及其组合。

7. 发明申请

US20050035460A1 Damascene structure and process at semiconductor substrate level 有权
标题翻译：大马士革结构和半导体衬底工艺
公开(公告)号：US20050035460A1
公开(公告)日：2005-02-17
申请号：US10640757
申请日：2003-08-14
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L23/485 , H01L21/4763 , H01L23/48
CPC分类号： H01L21/76846 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.
摘要翻译：半导体衬底级别的镶嵌结构和工艺。在半导体衬底上设置预金属电介质层，该开口露出衬底上的接触区域。在暴露的接触区域上设置有缓冲金属层，在开口的内部设有阻挡层。导体设置在缓冲金属层上，基本上填充开口以电连接到接触区域。

8. 发明授权

US06841466B1 Method of selectively making copper using plating technology 有权
标题翻译：使用电镀技术选择性制作铜的方法
公开(公告)号：US06841466B1
公开(公告)日：2005-01-11
申请号：US10672395
申请日：2003-09-26
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/7684 , H01L21/76879
摘要： A method of forming a more uniform copper interconnect layer is described. A dielectric layer, electroconductive (EC) layer, and a photoresist layer are sequentially deposited on a substrate. An opening in the photoresist is etched through the dielectric layer while the EC layer serves as a hard mask. Following deposition of a diffusion barrier layer and copper seed layer on the EC layer and in the opening, the copper seed layer is removed above the EC layer by a first CMP step. The EC layer serves as a CMP stop to protect the dielectric layer and provides a more uniform surface for subsequent steps. Copper is selectively deposited on the seed layer within the opening. A second CMP step lowers the copper layer to be coplanar with the dielectric layer and removes the EC layer. The resulting copper interconnect layer has a more uniform thickness and surface for improved performance.
摘要翻译：描述形成更均匀的铜互连层的方法。电介质层，导电（EC）层和光致抗蚀剂层顺序沉积在基片上。通过介电层蚀刻光致抗蚀剂中的开口，而EC层用作硬掩模。在EC层和开口中沉积扩散阻挡层和铜籽晶层之后，通过第一CMP步骤在EC层上方去除铜籽晶层。 EC层用作CMP阻挡层，以保护电介质层，并为后续步骤提供更均匀的表面。铜选择性地沉积在开口内的种子层上。第二CMP步骤降低铜层与电介质层共面并去除EC层。所得的铜互连层具有更均匀的厚度和表面以提高性能。

9. 发明授权

US06576555B2 Method of making upper conductive line in dual damascene having lower copper lines 有权
标题翻译：在具有较低铜线的双镶嵌中制造上导线的方法
公开(公告)号：US06576555B2
公开(公告)日：2003-06-10
申请号：US09755850
申请日：2001-01-05
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21311
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76844 , H01L21/76883
摘要： A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The processes begin from a substrate having lower copper conductive lines and a via formed in the nitride layer. An oxide layer plays as IMD is then formed on the nitride layer. Next, the oxide layer is patterned to form trenches. Thereafter, a barrier layer is deposited on the resulting exposed surface. An anisotropic etching process is then carried out to form barrier spacers on the sidewall of the trenches. Subsequently, an inert gas bombardment is done to remove a copper oxide layer so as to clean a surface of the via. Next, a conductive layer refilled in the trenches followed by a CMP process is successively performed to form a plurality of upper conductive lines.
摘要翻译：公开了一种在具有较低铜导线的双镶嵌工艺中制造上导电线的方法。该工艺从具有较低铜导电线和在氮化物层中形成的通孔的衬底开始。随后在氮化物层上形成IMD，氧化物层起作用。接下来，对氧化物层进行图案化以形成沟槽。此后，在所得到的暴露表面上沉积阻挡层。然后进行各向异性蚀刻工艺以在沟槽的侧壁上形成阻挡间隔物。随后，进行惰性气体轰击以除去氧化铜层以清洁通孔的表面。接下来，依次执行在沟槽中再填充的导电层，然后进行CMP处理，以形成多个上导电线。

10. 发明授权

US06531781B2 Fabrication of transistor having elevated source-drain and metal silicide 有权
公开(公告)号：US06531781B2
公开(公告)日：2003-03-11
申请号：US09734893
申请日：2000-12-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2348
CPC分类号： H01L29/66583 , H01L21/28518 , H01L21/28525 , H01L29/41783 , H01L29/66545 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a transistor, the method comprises following steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the doped amorphous silicon layer; removes the first dielectric layer to form a window; forms a second dielectric layer on both the metal silicide layer and the hole; and forms a conductor layer on the second dielectric layer. Significantly, during formation of the second dielectric layer, not only numerous dopants inside the doped amorphous silicon layer are driven into the substrate but also the doped amorphous silicon layer usually is re-crystallized to form an epi-like silicon layer.

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