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1. 发明授权

US09800218B1 Apparatus and method for correcting baseline wander and offset insertion in AC coupling circuits 有权
公开(公告)号：US09800218B1
公开(公告)日：2017-10-24
申请号：US15193716
申请日：2016-06-27
申请人： QUALCOMM Incorporated
发明人： Todd Morgan Rasmus
IPC分类号： H03F3/45 , H03G3/30
CPC分类号： H03F3/45183 , H03F3/45197 , H03F3/45475 , H03F3/45704 , H03F3/45757 , H03F3/45766 , H03F3/45959 , H03F3/45982 , H03F3/45991 , H03F2200/129 , H03F2200/21 , H03F2200/228 , H03F2200/375 , H03F2200/42 , H03F2203/45004 , H03F2203/45042 , H03F2203/45116 , H03F2203/45134 , H03F2203/45138 , H03F2203/45146 , H03F2203/45151 , H03F2203/45152 , H03F2203/45154 , H03F2203/45156 , H03F2203/45192 , H03F2203/45194 , H03F2203/45212 , H03F2203/45221 , H03F2203/45361 , H03F2203/45471 , H03F2203/45538 , H03F2203/45542 , H03F2203/45544 , H03F2203/45588 , H03F2203/45596 , H03G3/30
摘要： The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal. The compensation differential signal is applied to the output terminals of the first and second capacitors via a pair of resistors, respectively.

2. 发明申请

US20080143439A1 Fully-differential amplifier 有权
标题翻译：全差分放大器
公开(公告)号：US20080143439A1
公开(公告)日：2008-06-19
申请号：US11812378
申请日：2007-06-18
申请人： Hiroshi Tanimoto , Masayuki Katakura
发明人： Hiroshi Tanimoto , Masayuki Katakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45659 , H03F3/45748 , H03F3/45757 , H03F3/45973 , H03F3/45982 , H03F2200/513 , H03F2203/45082 , H03F2203/45088 , H03F2203/45134 , H03F2203/45212 , H03F2203/45526 , H03F2203/45644
摘要： A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.
摘要翻译：公开了能够在低电源电压下工作并提供共模信号抑制功能的全差分放大器。该全差分放大器配备有由单级配置反相放大器配置的第一全差分放大器，并且由前馈装置消除输入侧的共模信号，并且由单个配置反相放大器配置的第二全差分放大器级配置反相放大器，并通过反馈装置消除输出侧的共模信号，第一全差分放大器的输出连接到第二全差分放大器的输入端。

3. 发明授权

US4480231A Circuit for reducing offset voltage drift in differential amplifiers 失效
标题翻译：降低差分放大器偏移电压漂移的电路
公开(公告)号：US4480231A
公开(公告)日：1984-10-30
申请号：US411192
申请日：1982-08-25
申请人： Shigeru Takehara
发明人： Shigeru Takehara
IPC分类号： H03F3/45 , H03F1/26
CPC分类号： H03F3/45757 , H03F2203/45454
摘要： A differential pair of transistors is coupled to a current source and an active load to provide an output voltage which has little offset voltage drift with respect to input voltage variation. Biasing means establish a predetermined current which is supplied to the differential pair and which is varied by control means in response to the input signal to reduce offset voltage drift.
摘要翻译：晶体管的差分对耦合到电流源和有源负载以提供相对于输入电压变化几乎没有偏移电压漂移的输出电压。偏置装置建立供给差分对的预定电流，并响应于输入信号而由控制装置改变以减小偏移电压漂移。

4. 发明授权

US06556074B2 Differential amplifying circuit and multi-stage differential amplifying circuit using the same 失效
公开(公告)号：US06556074B2
公开(公告)日：2003-04-29
申请号：US10127877
申请日：2002-04-23
申请人： Yasufumi Suzuki
发明人： Yasufumi Suzuki
IPC分类号： G06G726
CPC分类号： H03F3/45183 , H03F3/45739 , H03F3/45757 , H03F2203/45364 , H03F2203/45652 , H03F2203/45691 , H03F2203/45694
摘要： A multi-stage differential amplifying circuit (100) is disclosed. Multi-stage differential amplifying circuit (100) may include initial stage differential amplifying circuits (SN1 and SP1). Initial stage amplifying circuits (SN1 and SP1) may receive an input signal at input terminals (H01 and H02) and provide a differential output signal at nodes (N9 and N13). An amplitude controlling transistor (ND) may provide a controllable impedance path between nodes (N9 and N13). Amplitude controlling transistor (ND) may have a control gate connected to a current supply node (N10). The controllable impedance path may be controlled so that a magnitude of a differential output signal at nodes (N9 and N13) may be more consistent even when an offset voltage of an input signal at input terminals (H01 and H02) varies. A next stage differential amplifying circuit (SOP) may receive the differential output signal at nodes (N9 and N13) and provide an output signal at an output terminal (N01).

5. 发明授权

US06496067B1 Class AB voltage current convertor having multiple transconductance stages and its application to power amplifiers 失效
标题翻译：具有多个跨导级的AB类电压电流转换器及其在功率放大器中的应用
公开(公告)号：US06496067B1
公开(公告)日：2002-12-17
申请号：US10041147
申请日：2002-01-07
申请人： Arya Reza Behzad , Li Lin
发明人： Arya Reza Behzad , Li Lin
IPC分类号： H03F345
CPC分类号： H03F1/3211 , H03F3/45757
摘要： A Class AB voltage-to-current converter includes a primary transconductance stage, secondary transconductance stage, and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the primary transconductance stage 12 becomes active before the secondary transconductance stage 14 with respect to the magnitude of a differential input voltage 18, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current convert.
摘要翻译： AB类电压 - 电流转换器包括初级跨导级，次级跨导级和偏置电路。偏置电路产生大于产生的次级偏置电压的初级偏置电压。因此，主跨导级12相对于差分输入电压18的幅度在次级跨导级14之前变为有效，从而允许将次级跨导级的跨导从主级跨导级的跨导增加（或减去）提高AB类电压 - 电流转换的整体跨导的阶段。

6. 发明授权

US06252460B1 FET balun transformer 有权
标题翻译：平衡不平衡变压器
公开(公告)号：US06252460B1
公开(公告)日：2001-06-26
申请号：US09480486
申请日：2000-01-11
申请人： Junji Ito
发明人： Junji Ito
IPC分类号： H03F304
CPC分类号： H03F3/45381 , H03F3/45757 , H03F3/45766 , H03F2203/45544 , H03F2203/45594 , H03F2203/45702 , H03F2203/45706
摘要： An inventive FET balun transformer uses a positive power supply alone, not a negative one, thus downsizing a device including the balun transformer. In the FET balun transformer, a voltage supplied from the positive power supply is divided by a voltage divider consisting of a pair of resistors. The gate of a first FET is biased at a positive voltage, which is obtained by getting the divided supply voltage further divided by a first resistor. The gate of a second FET is grounded with an AC grounded capacitor interposed therebetween and biased at a positive voltage, which is obtained by getting the divided supply voltage further divided by a second resistor. Thus, the gate and source of a third FET do not have to be set at a negative potential, but may be grounded directly and via a biasing resistor, respectively. As a result, no negative power supply is needed for the third FET and the single-ended signal received at the input terminal can be converted into differential signals, which will be output through output terminals, while using the positive power supply alone.
摘要翻译：本发明的平衡 - 不平衡转换变压器单独使用正电源，而不是负电源，从而使包括平衡不平衡变压器的装置小型化。在平衡不平衡变压器中，从正电源提供的电压由一对电阻分压器分压。第一FET的栅极被偏置为正电压，其通过使分压的电源电压进一步被第一电阻器分压而获得。第二FET的栅极通过置于其间的交流接地电容器接地，并且通过使分压电源电压进一步被第二电阻器分压而获得的正电压被偏置。因此，第三FET的栅极和源极不必被设置在负电位，而是可以分别直接地和通过偏置电阻器接地。结果，第三FET不需要负电源，并且在单独使用正电源的同时，可以将在输入端接收的单端信号转换成差分信号，这些差分信号将通过输出端输出。

7. 发明授权

US6137350A Differential amplifier circuit 有权
标题翻译：差分放大电路
公开(公告)号：US6137350A
公开(公告)日：2000-10-24
申请号：US172861
申请日：1998-10-15
申请人： Tadashi Maeda
发明人： Tadashi Maeda
IPC分类号： H03F3/45 , G06G7/12
CPC分类号： H03F3/45757 , H03F3/45385 , H03F2203/45702
摘要： The average value of an input signal supplied to an input terminal is generated by an integrating circuit consisting of a series circuit of a capacitor, a constant-current source transistor, and a resistor. The average value is used as the reference voltage for the differential amplifier circuit. Further, to each of differential pair transistors the sources of which are commonly connected, other transistors are cascode connected, respectively. Supplied to each gate of the cascode connected transistors is a divisional voltage of the differential voltage between the average voltage from the integrating circuit and the circuit power supply voltage, which divisional voltage is obtained by a capacitive divider circuit.
摘要翻译：通过由电容器，恒流源晶体管和电阻器的串联电路组成的积分电路产生提供给输入端子的输入信号的平均值。平均值用作差分放大器电路的参考电压。此外，对于其源极共同连接的每个差分对晶体管，其他晶体管分别被共源共栅连接。向共源共栅连接的晶体管的每个栅极提供的是积分电路的平均电压与电路电源电压之间的差分电压的分压，该分压是由电容分压电路获得的。

8. 发明授权

US08653829B2 Method and system for high gain auto-zeroing arrangement for electronic circuits 有权
标题翻译：电子电路高增益自动调零装置的方法和系统
公开(公告)号：US08653829B2
公开(公告)日：2014-02-18
申请号：US13307018
申请日：2011-11-30
申请人： Srinivas K. Pulijala
发明人： Srinivas K. Pulijala
IPC分类号： G01R35/00 , G01R31/00
CPC分类号： H03F3/45183 , H03F3/45757 , H03F3/505 , H03F2203/45318 , H03F2203/45352 , H03F2203/45648 , H03F2203/45702
摘要： A method and system for high gain auto-zeroing arrangement for electronic circuits. An auto-zero electronic circuit eliminates an offset associated with a test electronic circuit. The test electronic circuit includes a pair of input terminals configured to receive an input voltage signal and a pair of output terminals. The auto-zero electronic circuit includes a pair of source followers, and a pair of capacitors coupled to the output terminals of the test electronic circuit for sampling the offset associated with the test electronic circuit. The auto-zero electronic circuit also includes a differential pair coupled to the pair of source followers. A pair of diode-connected transistors, coupled to the differential pair, is configured to generate biasing voltage signals. The biasing voltage signals modulate the control terminals of a pair of input source followers of the test electronic circuit and eliminate the offset associated with the test electronic circuit.
摘要翻译：一种用于电子电路的高增益自动调零装置的方法和系统。自动归零电子电路消除了与测试电子电路相关的偏移。测试电子电路包括被配置为接收输入电压信号的一对输入端子和一对输出端子。自动归零电子电路包括一对源极跟随器和耦合到测试电子电路的输出端子的一对电容器，用于对与测试电子电路相关联的偏移进行采样。自动归零电子电路还包括耦合到一对源跟随器的差分对。耦合到差分对的一对二极管连接的晶体管被配置为产生偏置电压信号。偏置电压信号调制测试电子电路的一对输入源跟随器的控制端，并消除与测试电子电路相关的偏移。

9. 发明申请

US20130134988A1 METHOD AND SYSTEM FOR HIGH GAIN AUTO-ZEROING ARRANGEMENT FOR ELECTRONIC CIRCUITS 有权
标题翻译：用于电子电路的高增益自动调零装置的方法和系统
公开(公告)号：US20130134988A1
公开(公告)日：2013-05-30
申请号：US13307018
申请日：2011-11-30
申请人： Srinivas K. Pulijala
发明人： Srinivas K. Pulijala
IPC分类号： G01R35/00
CPC分类号： H03F3/45183 , H03F3/45757 , H03F3/505 , H03F2203/45318 , H03F2203/45352 , H03F2203/45648 , H03F2203/45702
摘要： A method and system for high gain auto-zeroing arrangement for electronic circuits. An auto-zero electronic circuit eliminates an offset associated with a test electronic circuit. The test electronic circuit includes a pair of input terminals configured to receive an input voltage signal and a pair of output terminals. The auto-zero electronic circuit includes a pair of source followers, and a pair of capacitors coupled to the output terminals of the test electronic circuit for sampling the offset associated with the test electronic circuit. The auto-zero electronic circuit also includes a differential pair coupled to the pair of source followers. A pair of diode-connected transistors, coupled to the differential pair, is configured to generate biasing voltage signals. The biasing voltage signals modulate the control terminals of a pair of input source followers of the test electronic circuit and eliminate the offset associated with the test electronic circuit.
摘要翻译：一种用于电子电路的高增益自动调零装置的方法和系统。自动归零电子电路消除了与测试电子电路相关的偏移。测试电子电路包括被配置为接收输入电压信号的一对输入端子和一对输出端子。自动归零电子电路包括一对源极跟随器和耦合到测试电子电路的输出端子的一对电容器，用于对与测试电子电路相关联的偏移进行采样。自动归零电子电路还包括耦合到一对源跟随器的差分对。耦合到差分对的一对二极管连接的晶体管被配置为产生偏置电压信号。偏置电压信号调制测试电子电路的一对输入源跟随器的控制端，并消除与测试电子电路相关的偏移。

10. 发明授权

US07619473B2 Fully-differential amplifier 有权
标题翻译：全差分放大器
公开(公告)号：US07619473B2
公开(公告)日：2009-11-17
申请号：US11812378
申请日：2007-06-18
申请人： Hiroshi Tanimoto , Masayuki Katakura
发明人： Hiroshi Tanimoto , Masayuki Katakura
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45659 , H03F3/45748 , H03F3/45757 , H03F3/45973 , H03F3/45982 , H03F2200/513 , H03F2203/45082 , H03F2203/45088 , H03F2203/45134 , H03F2203/45212 , H03F2203/45526 , H03F2203/45644
摘要： A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.
摘要翻译：公开了能够在低电源电压下工作并提供共模信号抑制功能的全差分放大器。该全差分放大器配备有由单级配置反相放大器配置的第一全差分放大器，并且由前馈装置消除输入侧的共模信号，并且由单个配置反相放大器配置的第二全差分放大器级配置反相放大器，并通过反馈装置消除输出侧的共模信号，第一全差分放大器的输出连接到第二全差分放大器的输入端。

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