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1. 发明授权

US08847683B2 Differential amplifying circuit 有权
标题翻译：差分放大电路
公开(公告)号：US08847683B2
公开(公告)日：2014-09-30
申请号：US13446698
申请日：2012-04-13
申请人： Noriaki Shirai
发明人： Noriaki Shirai
IPC分类号： H03F3/45
CPC分类号： H03F3/45 , H03F3/45179 , H03F3/45183 , H03F3/72 , H03F2203/45394 , H03F2203/45554 , H03F2203/45608 , H03F2203/45631 , H03F2203/45638 , H03F2203/45701 , H03F2203/45702 , H03F2203/45706 , H03F2203/45726
摘要： A differential amplifying circuit includes: two metal oxide semiconductor transistors to form a differential pair and receive a differential signal; a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors; and an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal.
摘要翻译：差分放大电路包括：两个金属氧化物半导体晶体管，用于形成差分对并接收差分信号; 串联耦合在两个金属氧化物半导体晶体管的漏极之间的多个电容元件; 以及耦合在所述多个电容元件中的至少一个连接节点与偏置电源端子之间的电感电路。

2. 发明授权

US08451058B2 Amplifier bandwidth extension for high-speed tranceivers 有权
公开(公告)号：US08451058B2
公开(公告)日：2013-05-28
申请号：US13166592
申请日：2011-06-22
申请人： Delong Cui , Afshin Momtaz , Jun Cao
发明人： Delong Cui , Afshin Momtaz , Jun Cao
IPC分类号： H03F3/16 , H03F3/04
CPC分类号： H03F3/16 , H03F1/42 , H03F3/195 , H03F3/45183 , H03F2200/336 , H03F2200/423 , H03F2203/45631 , H03F2203/45638 , H03F2203/45702 , H03F2203/45706
摘要： There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

3. 发明授权

US07176758B2 Multi-stage output buffer 有权
标题翻译：多级输出缓冲器
公开(公告)号：US07176758B2
公开(公告)日：2007-02-13
申请号：US10934164
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03B5/1209 , H03B5/1228 , H03B5/124 , H03F3/191 , H03F3/195 , H03F3/4508 , H03F3/50 , H03F2203/45704 , H03F2203/45706 , H03L7/099
摘要： A multi-stage output buffer is disclosed. The output buffer includes an emitter follower circuit coupled to a differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit. The buffer further includes a base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit reduces a load impedance at the output of the emitter coupled pair circuit, improves decoupling of the external load from an input circuit when coupled thereto, and increases the output power.
摘要翻译：公开了一种多级输出缓冲器。输出缓冲器包括耦合到差分输入的射极跟随器电路，其被配置为在其输入处提供基本上高的输入阻抗，并且在其输出处提供基本上低的输出阻抗。发射极耦合对电路耦合到射极跟随器电路的输出，并被配置为放大信号并进一步隔离输入电路。缓冲器还包括耦合到发射极耦合对电路的输出并具有耦合到多级输出缓冲器的差分输出的输出的基极接地配置晶体管电路。基极接地晶体管电路降低了发射极耦合对电路输出端的负载阻抗，改善了外部负载与输入电路耦合时的去耦耦合，并提高了输出功率。

4. 发明申请

US20050136847A1 Communication semiconductor integrated circuit device and electrical apparatus 审中-公开
标题翻译：通信半导体集成电路器件和电气设备
公开(公告)号：US20050136847A1
公开(公告)日：2005-06-23
申请号：US11011153
申请日：2004-12-15
申请人： Hiroaki Matsui , Taizo Yamawaki , Masahiro Ito , Masakatsu Yokota
发明人： Hiroaki Matsui , Taizo Yamawaki , Masahiro Ito , Masakatsu Yokota
IPC分类号： H03G11/00 , H03F1/32 , H03F1/52 , H03F3/195 , H03F3/45 , H03F3/72 , H03G3/10 , H03G3/30 , H04B1/44
CPC分类号： H03F3/45286 , H03F1/3211 , H03F1/52 , H03F3/195 , H03F3/72 , H03F2200/09 , H03F2200/111 , H03F2203/45638 , H03F2203/45704 , H03F2203/45706 , H03G3/3042
摘要： A communication semiconductor integrated circuit (high frequency IC) that has a function of differentially-singly converts and outputs a transmitted signal suppressing deterioration of a harmonic suppression characteristic and enables miniaturization and an electronic component (high frequency module) that mounts the communication semiconductor integrated circuit are provided. In the communication semiconductor integrated circuit (high frequency IC) having a limiter that amplifies a modulated and up-converted transmitted signal and supplies a power amplifier with the signal, an unbalanced reduction means having, for example, differential MOS transistors is provided in collectors or drains of differential transistors that construct the limiter to output pins and continue to apply a current to the output pins and reduces the impedance of the transistor on an off side even when one of the transistors enters an off state in accordance with an input signal in parallel to the transistor.
摘要翻译：具有差分单变换功能的通信用半导体集成电路（高频IC），输出抑制谐波抑制特性的劣化的发送信号，能够实现小型化，以及安装通信半导体集成电路的电子部件（高频模块）被提供。在具有放大经调制和上变频的发送信号并向功率放大器供给该信号的限幅器的通信半导体集成电路（高频IC）中，具有例如差分MOS晶体管的不平衡减小装置设置在收集器或差分晶体管的漏极构成限制器以输出引脚并且继续向输出引脚施加电流，并且即使当晶体管中的一个根据并行的输入信号进入截止状态时也减小了晶体管在截止侧的阻抗到晶体管。

5. 发明申请

US20130057350A1 Apparatus and Method for Low Noise Amplification 有权
标题翻译：低噪声放大装置及方法
公开(公告)号：US20130057350A1
公开(公告)日：2013-03-07
申请号：US13224430
申请日：2011-09-02
申请人： Jonne Juhani RIEKKI , Jari Johannes Heikkinen , Jouni Kristian Kaukovuori
发明人： Jonne Juhani RIEKKI , Jari Johannes Heikkinen , Jouni Kristian Kaukovuori
IPC分类号： H03F1/08 , H04R31/00
CPC分类号： H03F1/56 , H03F3/211 , H03F3/45183 , H03F2200/294 , H03F2200/318 , H03F2203/45481 , H03F2203/45706 , Y10T29/49005
摘要： Embodiments provide an amplifier and a method for using and manufacturing said amplifier that incorporate an impedance matching stage, a feedback circuit, and a gain stage. The impedance matching stage is coupled to the feedback circuit wherein the feedback circuit provides a compensated operating voltage for the impedance matching stage. The output of the impedance matching stage is used to set an input bias voltage for both the impedance matching stage and the gain stage. The output of the impedance matching stage is also used, together with the output of the gain stage, to produce an output of the amplifier.
摘要翻译：实施例提供一种用于使用和制造并入有阻抗匹配级，反馈电路和增益级的所述放大器的放大器和方法。阻抗匹配级耦合到反馈电路，其中反馈电路为阻抗匹配级提供经补偿的工作电压。阻抗匹配级的输出用于设置阻抗匹配级和增益级的输入偏置电压。还使用阻抗匹配级的输出以及增益级的输出来产生放大器的输出。

6. 发明申请

US20120262236A1 DIFFERENTIAL AMPLIFYING CIRCUIT 有权
标题翻译：差分放大电路
公开(公告)号：US20120262236A1
公开(公告)日：2012-10-18
申请号：US13446698
申请日：2012-04-13
申请人： Noriaki SHIRAI
发明人： Noriaki SHIRAI
IPC分类号： H03F3/45
CPC分类号： H03F3/45 , H03F3/45179 , H03F3/45183 , H03F3/72 , H03F2203/45394 , H03F2203/45554 , H03F2203/45608 , H03F2203/45631 , H03F2203/45638 , H03F2203/45701 , H03F2203/45702 , H03F2203/45706 , H03F2203/45726
摘要： A differential amplifying circuit includes: two metal oxide semiconductor transistors to form a differential pair and receive a differential signal; a plurality of capacitance elements coupled in series between drains of the two metal oxide semiconductor transistors; and an inductance circuit coupled between at least one connection node of the plurality of capacitance elements and a bias power terminal.
摘要翻译：差分放大电路包括：两个金属氧化物半导体晶体管，用于形成差分对并接收差分信号; 串联耦合在两个金属氧化物半导体晶体管的漏极之间的多个电容元件; 以及耦合在所述多个电容元件中的至少一个连接节点与偏置电源端子之间的电感电路。

7. 发明授权

US07170349B2 Low voltage broadband gain cell 有权
标题翻译：低电压宽带增益电池
公开(公告)号：US07170349B2
公开(公告)日：2007-01-30
申请号：US10946738
申请日：2004-09-21
申请人： Jishnu Bhattacharjee , Debanjan Mukherjee
发明人： Jishnu Bhattacharjee , Debanjan Mukherjee
IPC分类号： H03F3/45
CPC分类号： H03F1/42 , H03F3/45183 , H03F3/45188 , H03F2200/39 , H03F2203/45361 , H03F2203/45638 , H03F2203/45641 , H03F2203/45652 , H03F2203/45686 , H03F2203/45702 , H03F2203/45704 , H03F2203/45706 , H03F2203/45731
摘要： T-coil structures are used in one embodiment to inject programmably-variable amounts of transistor biasing currents into the respective drains of current sinking transistor means of a broadband differential amplifier such that, when the differential amplifier is in common mode, total transistor drain current will exceed total voltage-dropping current passing through corresponding voltage-dropping resistances of the amplifier's transistor means. The T-coil structures keep the parasitic capacitances of the programmable current sources that provide the bias currents de-lumped from capacitances of the amplifier's output nodes and/or capacitances of the amplifier's voltage-dropping resistances (variable resistances) to thereby maintain a wide bandwidth.
摘要翻译：在一个实施例中使用T形线圈结构，以将可编程可变量的晶体管偏置电流注入到宽带差分放大器的电流吸收晶体管装置的相应漏极中，使得当差分放大器处于共模时，总晶体管漏极电流将超过通过放大器晶体管装置的相应降压电阻的总压降电流。 T线圈结构保持可编程电流源的寄生电容，其提供从放大器的输出节点的电容和/或放大器的降压电阻（可变电阻）的电容中解除的偏置电流，从而保持宽带宽。

8. 发明申请

US20060049871A1 Multi-stage output buffer 有权
标题翻译：多级输出缓冲器
公开(公告)号：US20060049871A1
公开(公告)日：2006-03-09
申请号：US10934164
申请日：2004-09-03
申请人： Hans-Martin Rein , Hao Li
发明人： Hans-Martin Rein , Hao Li
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03B5/1209 , H03B5/1228 , H03B5/124 , H03F3/191 , H03F3/195 , H03F3/4508 , H03F3/50 , H03F2203/45704 , H03F2203/45706 , H03L7/099
摘要： A multi-stage output buffer is disclosed having a differential input and a differential output. The output buffer includes an emitter follower circuit coupled to the differential input that is configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof. An emitter coupled pair circuit is coupled to the output of the emitter follower circuit, and is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof. The buffer further includes a base-grounded transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer. The base-grounded transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed thereof. The base-grounded transistor circuit further improves decoupling of the external load from an input circuit when coupled thereto and increases the output power.
摘要翻译：公开了具有差分输入和差分输出的多级输出缓冲器。输出缓冲器包括耦合到差分输入的射极跟随器电路，其被配置为在其输入处提供基本上高的输入阻抗，并且在其输出处提供基本上低的输出阻抗。发射极耦合对电路耦合到射极跟随器电路的输出端，并且被配置为放大信号并进一步隔离输入电路，当耦合到与多级输出缓冲器的差分输入耦合到多级输出缓冲器差分输出。缓冲器还包括耦合到发射极耦合对电路的输出的基极接地晶体管电路，并且具有耦合到多级输出缓冲器的差分输出的输出。基极接地晶体管电路被配置为减小发射极耦合对电路的输出处的负载阻抗，从而提高其速度。基极接地晶体管电路进一步改善外部负载与输入电路耦合时的去耦耦合，并提高输出功率。

9. 发明授权

US09473091B2 Amplifier with common-mode filter 有权
标题翻译：具有共模滤波器的放大器
公开(公告)号：US09473091B2
公开(公告)日：2016-10-18
申请号：US14620823
申请日：2015-02-12
申请人： QUALCOMM Incorporated
发明人： Muhammad Hassan , Bhushan Shanti Asuri , Apsara Ravish Suvarna , Youngchang Yoon
IPC分类号： H03F3/45 , H03F1/22
CPC分类号： H03F3/45632 , H03F1/223 , H03F3/245 , H03F3/45188 , H03F2200/09 , H03F2200/378 , H03F2203/45024 , H03F2203/45082 , H03F2203/45084 , H03F2203/45204 , H03F2203/45481 , H03F2203/45631 , H03F2203/45638 , H03F2203/45706 , H03F2203/45731
摘要： A differential amplifier having a tunable filter is disclosed. The tunable filter may attenuate some common-mode signals while not affecting amplification of differential signals. The tunable filter may include a resonant circuit to select frequencies of common-mode signals to attenuate. The resonant circuit may include a variable capacitor series-coupled to an inductor. A resonant frequency of the resonant circuit may be determined, in part, by a capacitance value of the variable capacitor.
摘要翻译：公开了一种具有可调谐滤波器的差分放大器。可调谐滤波器可以衰减一些共模信号，而不影响差分信号的放大。可调滤波器可以包括谐振电路，以选择共模信号的频率来衰减。谐振电路可以包括串联耦合到电感器的可变电容器。谐振电路的谐振频率可以部分地由可变电容器的电容值确定。

10. 发明授权

US08928355B2 Amplifier bandwidth extension for high-speed tranceivers 有权
标题翻译：用于高速收发器的放大器带宽扩展
公开(公告)号：US08928355B2
公开(公告)日：2015-01-06
申请号：US13867883
申请日：2013-04-22
申请人： Broadcom Corporation
发明人： Delong Cui , Afshin Momtaz , Jun Cao
IPC分类号： H03K19/094 , H03F3/16 , H03F1/42 , H03F3/195 , H03F3/45
CPC分类号： H03F3/16 , H03F1/42 , H03F3/195 , H03F3/45183 , H03F2200/336 , H03F2200/423 , H03F2203/45631 , H03F2203/45638 , H03F2203/45702 , H03F2203/45706
摘要： There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.
摘要翻译：为高速收发器提供了高带宽电路。该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。

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