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1. 发明申请

US20170141760A1 BASEBAND FILTERS AND INTERFACES BETWEEN A DIGITAL-TO-ANALOG CONVERTER AND A BASEBAND FILTER 有权
公开(公告)号：US20170141760A1
公开(公告)日：2017-05-18
申请号：US14941419
申请日：2015-11-13
申请人： QUALCOMM Incorporated
发明人： Ibrahim Chamas
IPC分类号： H03H11/12 , H03F3/19 , H03F3/21 , H03M1/66 , H03F3/45
CPC分类号： H03H11/1213 , H03F1/08 , H03F1/3205 , H03F1/3241 , H03F1/342 , H03F3/19 , H03F3/195 , H03F3/211 , H03F3/45076 , H03F3/45659 , H03F2200/144 , H03F2200/171 , H03F2200/237 , H03F2200/24 , H03F2200/294 , H03F2200/451 , H03F2200/72 , H03F2200/75 , H03F2200/91 , H03F2203/21106 , H03F2203/21115 , H03F2203/21157 , H03F2203/45002 , H03F2203/45004 , H03F2203/45126 , H03F2203/45154 , H03H11/126 , H03M1/66
摘要： Exemplary embodiments of the present disclosure are related to baseband filters. A device may include a digital-to-analog converter (DAC) configured to output a DC current. The device may also include an operational amplifier coupled to an output of the DAC and configured to bias an input stage of the operational amplifier with the DC current.

2. 发明授权

US09800218B1 Apparatus and method for correcting baseline wander and offset insertion in AC coupling circuits 有权
公开(公告)号：US09800218B1
公开(公告)日：2017-10-24
申请号：US15193716
申请日：2016-06-27
申请人： QUALCOMM Incorporated
发明人： Todd Morgan Rasmus
IPC分类号： H03F3/45 , H03G3/30
CPC分类号： H03F3/45183 , H03F3/45197 , H03F3/45475 , H03F3/45704 , H03F3/45757 , H03F3/45766 , H03F3/45959 , H03F3/45982 , H03F3/45991 , H03F2200/129 , H03F2200/21 , H03F2200/228 , H03F2200/375 , H03F2200/42 , H03F2203/45004 , H03F2203/45042 , H03F2203/45116 , H03F2203/45134 , H03F2203/45138 , H03F2203/45146 , H03F2203/45151 , H03F2203/45152 , H03F2203/45154 , H03F2203/45156 , H03F2203/45192 , H03F2203/45194 , H03F2203/45212 , H03F2203/45221 , H03F2203/45361 , H03F2203/45471 , H03F2203/45538 , H03F2203/45542 , H03F2203/45544 , H03F2203/45588 , H03F2203/45596 , H03G3/30
摘要： The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal. The compensation differential signal is applied to the output terminals of the first and second capacitors via a pair of resistors, respectively.

3. 发明授权

US09647639B1 Baseband filters and interfaces between a digital-to-analog converter and a baseband filter 有权
公开(公告)号：US09647639B1
公开(公告)日：2017-05-09
申请号：US14941419
申请日：2015-11-13
申请人： QUALCOMM Incorporated
发明人： Ibrahim Chamas
IPC分类号： H03K5/00 , H03F3/45 , H03H11/12 , H03M1/66 , H03F3/21 , H03F3/19
CPC分类号： H03H11/1213 , H03F1/08 , H03F1/3205 , H03F1/3241 , H03F1/342 , H03F3/19 , H03F3/195 , H03F3/211 , H03F3/45076 , H03F3/45659 , H03F2200/144 , H03F2200/171 , H03F2200/237 , H03F2200/24 , H03F2200/294 , H03F2200/451 , H03F2200/72 , H03F2200/75 , H03F2200/91 , H03F2203/21106 , H03F2203/21115 , H03F2203/21157 , H03F2203/45002 , H03F2203/45004 , H03F2203/45126 , H03F2203/45154 , H03H11/126 , H03M1/66
摘要： Exemplary embodiments of the present disclosure are related to baseband filters. A device may include a digital-to-analog converter (DAC) configured to output a DC current. The device may also include an operational amplifier coupled to an output of the DAC and configured to bias an input stage of the operational amplifier with the DC current.

4. 发明授权

US5491455A Differential-to-single ended translator that generates an output signal with very small signal distortion 失效
标题翻译：差分到单端转换器，产生具有非常小的信号失真的输出信号
公开(公告)号：US5491455A
公开(公告)日：1996-02-13
申请号：US337259
申请日：1994-11-10
申请人： James R. Kuo
发明人： James R. Kuo
IPC分类号： H03F1/32 , H03F3/45 , H03K5/24
CPC分类号： H03F3/45179 , H03F1/3211 , H03F3/45076 , H03F3/4521 , H03K5/2481 , H03F2203/45004 , H03F2203/45051 , H03F2203/45188 , H03F2203/45241 , H03F2203/45466
摘要： A translator circuit amplifies a pair of differential input signals to produce a pair of intermediate differential signals by utilizing a pair of cross-coupled differential gain stages. The gain stages amplify the input signals to balance the capacitive loading. The pair of intermediate differential signals are formed to be substantially equal and 180.degree. out of phase. The current sources of the gain stages are connected together and controlled by the outputs of the gain stages to reduce the rise and fall times of the intermediate differential signals. The translator circuit also converts the pair of intermediate differential signals to a single-ended output signal by utilizing a first differential pair to produce the output signal, and a second differential pair to adaptively control the current source of the first differential pair, thereby reducing the rise and fall times of the output signal. As a result, the translator circuit is capable of producing the output signal with minimum distortion. Therefore, a duty cycle of approximately 50% can be achieved.
摘要翻译：转换器电路通过利用一对交叉耦合的差分增益级来放大一对差分输入信号以产生一对中间差分信号。增益级放大输入信号以平衡电容负载。一对中间差分信号形成为大致相等且相位相差180度。增益级的电流源连接在一起，并由增益级的输出控制，以减少中间差分信号的上升和下降时间。转换器电路还通过利用第一差分对来产生输出信号而将一对中间差分信号转换为单端输出信号，以及第二差分对以自适应地控制第一差分对的电流源，从而减少上升和下降的输出信号的时间。结果，转换器电路能够产生具有最小失真的输出信号。因此，可以实现约50％的占空比。

5. 发明授权

US5229664A Programmable differentiator delay 失效
标题翻译：可编程差分延迟
公开(公告)号：US5229664A
公开(公告)日：1993-07-20
申请号：US725864
申请日：1991-07-03
申请人： Kevin E. Brehmer
发明人： Kevin E. Brehmer
IPC分类号： G11B5/09 , G11B20/10 , H03F3/45
CPC分类号： H03F3/45179 , G11B20/10009 , H03F3/45085 , H03F3/45278 , H03F3/45511 , H03F2200/219 , H03F2203/45004 , H03F2203/45076 , H03F2203/45082 , H03F2203/45144 , H03F2203/45201 , H03F2203/45244 , H03F2203/45362 , H03F2203/45366 , H03F2203/45641 , H03F2203/45646 , H03F2203/45648 , H03F2203/45712 , H03F2203/45732
摘要： A programmable delay for the gate signal output of the differentiator in a data analyzing circuit is provided. A data signal is produced by a low pass filter, and a differentiator (high pass filter) produces a gate signal. The cutoff frequency of the low pass filter is controlled by a first control circuit, and a second control circuit is provided to separately control the cutoff frequency of the high pass filter. The second control circuit produces a variation from the base frequency determined by the first control circuit. Thus, the cutoff frequency of the high pass filter will always be proportional to that of the low pass filter.

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