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1. 发明授权

US06366162B1 Multi-impedance input stage 失效
标题翻译：多阻抗输入级
公开(公告)号：US06366162B1
公开(公告)日：2002-04-02
申请号：US09753145
申请日：2001-01-02
申请人： Chris W. Angell , Erik L. Bengtsson , Scott R. Justice , Aristotele Hadjichristos
发明人： Chris W. Angell , Erik L. Bengtsson , Scott R. Justice , Aristotele Hadjichristos
IPC分类号： G06G726
CPC分类号： H03F1/56 , H03F3/45089 , H03F3/72 , H03F2200/432 , H03F2203/45596 , H03F2203/45702 , H03F2203/7203 , H03F2203/7236
摘要： An input buffer circuit is operable to selectively present either low or high input impedance while maintaining uniform output impedance. The buffer is characterized by first and second amplifier circuits connected in parallel between an input to and an output from the buffer. The amplifiers are individually controlled between enabled and disabled states. When enabled, the first amplifier has low input impedance and predetermined output impedance and the second amplifier has high input impedance and the predetermined output impedance, and when disabled each amplifier has high input and output impedance. To operate the buffer to have low input impedance, the first amplifier is enabled while the second amplifier is disabled. To operate the buffer to have high input impedance, the second amplifier is enabled while the first amplifier is disabled. When an amplifier is disabled, its input and output impedances are sufficiently large that the disabled amplifier does not interfere with operation of the enabled amplifier.
摘要翻译：输入缓冲器电路可操作以选择性地呈现低或高输入阻抗，同时保持均匀的输出阻抗。缓冲器的特征在于在缓冲器的输入和输出之间并联连接的第一和第二放大器电路。放大器在启用和禁用状态之间单独控制。当使能时，第一放大器具有低输入阻抗和预定的输出阻抗，第二放大器具有高输入阻抗和预定输出阻抗，并且禁用时，每个放大器具有高输入和输出阻抗。为了使缓冲器工作，具有低输入阻抗，第一个放大器使能，而第二个放大器被禁用。为了操作缓冲区具有高输入阻抗，第二个放大器在第一个放大器禁用时使能。当禁止放大器时，其输入和输出阻抗足够大，使得禁用的放大器不会干扰使能放大器的工作。

2. 发明授权

US06657486B2 MOS differential amplifier circuit having a wide linear input voltage range 有权
标题翻译： MOS差分放大电路具有宽线性输入电压范围
公开(公告)号：US06657486B2
公开(公告)日：2003-12-02
申请号：US10234129
申请日：2002-09-05
申请人： Katsuji Kimura
发明人： Katsuji Kimura
IPC分类号： G06G726
CPC分类号： H03F3/45717 , G06G7/14 , H03F3/45183 , H03F3/4565 , H03F3/4569 , H03F3/45708 , H03F3/45739 , H03F2203/45456 , H03F2203/45484 , H03F2203/45566 , H03F2203/45612 , H03F2203/45702
摘要： A MOS differential amplifier circuit has a differential pair having first and second MOS transistors. The source electrodes of the first and second MOS transistors are commonly coupled and driven by a current source, which can be adjusted to change the transconductance of the amplifier. The circuit can be provided with a quadri-tall cell or level shifter in order to provide this operation. With these operational characteristics, the MOS differential pair of this type can be used in a voltage adder/subtractor circuit.
摘要翻译： MOS差分放大器电路具有具有第一和第二MOS晶体管的差分对。第一和第二MOS晶体管的源极通常由电流源耦合和驱动，电流源可以被调节以改变放大器的跨导。为了提供这种操作，该电路可以设置有四节细胞或电平移位器。利用这些操作特性，这种类型的MOS差分对可以用在电压加法器/减法器电路中。

3. 发明授权

US06556074B2 Differential amplifying circuit and multi-stage differential amplifying circuit using the same 失效
公开(公告)号：US06556074B2
公开(公告)日：2003-04-29
申请号：US10127877
申请日：2002-04-23
申请人： Yasufumi Suzuki
发明人： Yasufumi Suzuki
IPC分类号： G06G726
CPC分类号： H03F3/45183 , H03F3/45739 , H03F3/45757 , H03F2203/45364 , H03F2203/45652 , H03F2203/45691 , H03F2203/45694
摘要： A multi-stage differential amplifying circuit (100) is disclosed. Multi-stage differential amplifying circuit (100) may include initial stage differential amplifying circuits (SN1 and SP1). Initial stage amplifying circuits (SN1 and SP1) may receive an input signal at input terminals (H01 and H02) and provide a differential output signal at nodes (N9 and N13). An amplitude controlling transistor (ND) may provide a controllable impedance path between nodes (N9 and N13). Amplitude controlling transistor (ND) may have a control gate connected to a current supply node (N10). The controllable impedance path may be controlled so that a magnitude of a differential output signal at nodes (N9 and N13) may be more consistent even when an offset voltage of an input signal at input terminals (H01 and H02) varies. A next stage differential amplifying circuit (SOP) may receive the differential output signal at nodes (N9 and N13) and provide an output signal at an output terminal (N01).

4. 发明授权

US06452445B1 Voltage controlled variable gain element 有权
标题翻译：电压可变增益元件
公开(公告)号：US06452445B1
公开(公告)日：2002-09-17
申请号：US09594988
申请日：2000-06-15
申请人： Dan Nobbe , Arul M. Balasubramaniyan
发明人： Dan Nobbe , Arul M. Balasubramaniyan
IPC分类号： G06G726
CPC分类号： H03G1/0023
摘要： A variable gain element for adjusting a magnitude of an input signal. The variable gain element includes a first differential transistor pair having a first transistor coupled to a second transistor. A second differential transistor pair couples the second transistor to a supply voltage and to an output terminal of the first transistor. A load resistor couples the output terminal to the supply voltage. A control voltage applied to an input of the second differential pair causes a varying amount of current cancellation through the load resistor.
摘要翻译：用于调整输入信号幅度的可变增益元件。可变增益元件包括具有耦合到第二晶体管的第一晶体管的第一差分晶体管对。第二差分晶体管对将第二晶体管耦合到电源电压和第一晶体管的输出端。负载电阻将输出端子耦合到电源电压。施加到第二差分对的输入端的控制电压通过负载电阻引起电流消除的变化量。

5. 发明授权

US06819168B1 Integrator with high gain and fast transient response 有权
标题翻译：具有高增益和快速瞬态响应的积分器
公开(公告)号：US06819168B1
公开(公告)日：2004-11-16
申请号：US10294853
申请日：2002-11-14
申请人： Robert John Brewer
发明人： Robert John Brewer
IPC分类号： G06G726
CPC分类号： H03F3/45183 , H03F3/211 , H03F2200/264 , H03F2203/45248 , H03H11/0466
摘要： A multi-stage integrator achieves a relatively high small-signal gain, broad bandwidth, and very clean transient pulse response. Only simple amplifying stages (typically including an inverting amplifier(s)) are used. A high gain amplifier is coupled between an integrator input node and amplifier output node. A broadband single stage amplifier (which may comprise or act as a transconductor), may act as a current source for the output transistor and load, coupled between the integrator input node and output node. Preferably, a capacitance is coupled from the integrator input to the amplifier output. A frequency-selective element or network steers signal components to the single stage amplifier or the integrator appropriately to produce a combined output that has the desired characteristics.
摘要翻译：多级积分器实现了相对较高的小信号增益，宽带宽和非常干净的瞬态脉冲响应。仅使用简单的放大级（通常包括反相放大器）。高增益放大器耦合在积分器输入节点和放大器输出节点之间。宽带单级放大器（其可以包括或用作跨导体）可以作为输出晶体管和负载的电流源，耦合在积分器输入节点和输出节点之间。优选地，电容从积分器输入耦合到放大器输出。频率选择元件或网络将信号分量适当地引导到单级放大器或积分器以产生具有期望特性的组合输出。

6. 发明授权

US06744308B1 System and method for establishing the input impedance of an amplifier in a stacked configuration 有权
标题翻译：用于在堆叠配置中建立放大器的输入阻抗的系统和方法
公开(公告)号：US06744308B1
公开(公告)日：2004-06-01
申请号：US10232348
申请日：2002-08-30
申请人： Kim E. Beumer
发明人： Kim E. Beumer
IPC分类号： G06G726
CPC分类号： H03F3/45085 , H03F2200/294 , H03F2200/372
摘要： A circuit for establishing the input impedance of an amplifier includes an amplifier, a circuit component, a first feedback resistor, and a second feedback resistor. The amplifier has an input impedance and is coupled to a load having a load impedance. The circuit component is coupled to the load and shares at least a portion of a bias current with the amplifier. The first feedback resistor is coupled the amplifier and the load, and has a first impedance. The second feedback resistor is coupled to the amplifier and has a second impedance. The input impedance of the amplifier is established based at least in part upon the first impedance and the second impedance.
摘要翻译：用于建立放大器的输入阻抗的电路包括放大器，电路部件，第一反馈电阻器和第二反馈电阻器。放大器具有输入阻抗并且耦合到具有负载阻抗的负载。电路部件耦合到负载并且与放大器共享至少一部分偏置电流。第一个反馈电阻耦合放大器和负载，并具有第一个阻抗。第二反馈电阻器耦合到放大器并且具有第二阻抗。至少部分地基于第一阻抗和第二阻抗建立放大器的输入阻抗。

7. 发明授权

US06411159B1 Circuit for controlling current levels in differential logic circuitry 有权
标题翻译：用于控制差分逻辑电路中电流电平的电路
公开(公告)号：US06411159B1
公开(公告)日：2002-06-25
申请号：US09620786
申请日：2000-07-21
申请人： Michael J. Callahan, Jr.
发明人： Michael J. Callahan, Jr.
IPC分类号： G06G726
CPC分类号： G05F3/242
摘要： A method and circuit are disclosed for controlling the current level of a differential logic circuit having a current source, input transistors which perform current steering based upon the input to the differential logic circuit, and load transistors. The circuit includes a first transistor that forms a current mirror with the current source, a second transistor coupled to the load transistors so that the operating characteristics of the load transistors substantially match the operating characteristics of the second transistor, and current source circuitry coupled between the first and second transistors. The current level selected in the current source circuitry sets the current level in the differential logic circuit and the resistance of the load transistors so that the output voltage swing of the differential logic circuit stays within an acceptable range of voltages, regardless of the selected current level.
摘要翻译：公开了一种用于控制具有电流源的差分逻辑电路的电流电平的方法和电路，基于对差分逻辑电路的输入和负载晶体管执行电流转向的输入晶体管。电路包括与电流源形成电流镜的第一晶体管，耦合到负载晶体管的第二晶体管，使得负载晶体管的工作特性基本上与第二晶体管的工作特性相匹配，并且电流源电路第一和第二晶体管。在电流源电路中选择的电流电平设置差分逻辑电路中的电流电平和负载晶体管的电阻，使得差分逻辑电路的输出电压摆幅保持在可接受的电压范围内，而与所选电流水平无关。

8. 发明授权

US06819170B1 Apparatus for sensing differential voltages with high common-mode levels 有权
标题翻译：用于感测高共模电平的差分电压的装置
公开(公告)号：US06819170B1
公开(公告)日：2004-11-16
申请号：US10327715
申请日：2002-12-20
申请人： Willem Johannes Kindt
发明人： Willem Johannes Kindt
IPC分类号： G06G726
CPC分类号： H03F3/45959 , H03F3/45968 , H03F2203/45614 , H03F2203/45724
摘要： A differential voltage amplifier includes a dynamic level shifter circuit and an amplifier circuit. The dynamic level shifter circuit includes high-impedance current sources and resistors that are arranged to move the common-mode levels of a differential input signal to a signal level that is suitable for the amplifier circuit. The amplifier circuit may be single-ended or differential. The dynamic level shifter circuit may include one or more current sources that are arranged to provide improved performance for low common-mode levels. A dynamic biasing scheme may be employed to improve operation over varied common-mode ranges. A trimming circuit may be used to adjust offsets in the system. A DC chop arrangement may be employed to remove offsets in the system.
摘要翻译：差分电压放大器包括动态电平移位器电路和放大器电路。动态电平移位器电路包括高阻抗电流源和电阻器，其被布置为将差分输入信号的共模电平移动到适合于放大器电路的信号电平。放大器电路可以是单端或差分。动态电平移位器电路可以包括一个或多个电流源，其被布置为为低共模电平提供改进的性能。可以采用动态偏置方案来改善在不同共模范围内的操作。调整电路可用于调整系统中的偏移量。可以采用直流斩波装置来去除系统中的偏移。

9. 发明授权

US06801080B1 CMOS differential input buffer with source-follower input clamps 失效
标题翻译： CMOS差分输入缓冲器，带有源极跟随器输入钳位
公开(公告)号：US06801080B1
公开(公告)日：2004-10-05
申请号：US10249414
申请日：2003-04-07
申请人： Christopher G. Arcus
发明人： Christopher G. Arcus
IPC分类号： G06G726
CPC分类号： H03K5/08 , H03K5/2481
摘要： A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.
摘要翻译：差分输入缓冲器显示对输入条件（如输入跟踪加载和上游驱动程序特性）的灵敏度降低。可以将输入条件改变为幅度，转换速率和共模偏移的差异。通过输入钳位电路将宽输入电压摆幅钳位到有限的电压范围，输入钳位电路使用源极跟随器驱动输入电压过低时关断的p沟道钳位晶体管。然后分压器将最低电压输入设置到差分级。差分级接收钳位输入，并具有两个尾电流吸收器，以减少对尾电容充电和放电的延迟灵敏度。中间电压被施加到与接收钳位的输入电压的差分晶体管相对的晶体管。通过镜像电流产生尾电流吸收器的偏置电压，并通过从电阻器注入和去除相同的偏置电流来设置栅极电压。

10. 发明授权

US06538501B2 Radio frequency amplifier and tuner 失效
标题翻译：射频放大器和调谐器
公开(公告)号：US06538501B2
公开(公告)日：2003-03-25
申请号：US09852600
申请日：2001-05-10
申请人： Arshad Madni
发明人： Arshad Madni
IPC分类号： G06G726
CPC分类号： H03F3/45085 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03F3/3432 , H03F2200/294 , H03F2200/372 , H03F2203/45318 , H03F2203/45392 , H03F2203/45508 , H03F2203/45701
摘要： A radio frequency amplifier includes first and second transconductance stages 20, 21, the product of whose transconductances is negative. The input and output of the first stage form the input and output of the amplifier. The output of the first stage is provided with a load 22 whereas the output of the second stage 21 is provided with a load 23 and is fed back to the input of the first stage.
摘要翻译：射频放大器包括第一和第二跨导级20,21，其跨导是负的乘积。第一级的输入和输出形成放大器的输入和输出。第一级的输出设有负载22，而第二级21的输出设有负载23，并被反馈到第一级的输入端。

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