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1. 发明授权

US10061584B2 Store nullification in the target field 有权
公开(公告)号：US10061584B2
公开(公告)日：2018-08-28
申请号：US15060404
申请日：2016-03-03
申请人： Microsoft Technology Licensing, LLC
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/312 , G06F9/44 , G06F9/30 , G06F15/80 , G06F9/32 , G06F9/38 , G06F9/26 , G06F11/36 , G06F12/0862 , G06F9/35 , G06F12/1009 , G06F13/42 , G06F15/78 , G06F9/46 , G06F9/52 , G06F12/0875 , G06F12/0811 , G06F12/0806
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.

2. 发明授权

US09959121B2 Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers 有权
公开(公告)号：US09959121B2
公开(公告)日：2018-05-01
申请号：US15013018
申请日：2016-02-02
申请人： International Business Machines Corporation
发明人： Christopher M. Abernathy , Mary D. Brown , Sundeep Chadha , Dung Q. Nguyen
IPC分类号： G06F9/34 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/30101 , G06F9/3012 , G06F9/30138 , G06F9/3016 , G06F9/34 , G06F9/3826 , G06F9/384
摘要： A register file bypass controller in communication with a set of one or more bypass registers, the register file bypass controller configured to receive a register file bypass request; determine whether to grant the register file bypass request; determine whether data identified by the register file bypass request is present in the set of one or more bypass registers in response to determining to grant the register file bypass request; determine a selected bypass register in the set of one or more bypass registers in response to determining the data identified by the register file bypass request is not present in the set of one or more bypass registers; determine to store the data identified by the register file bypass request in the selected bypass register; and notify an execution unit to cancel instruction execution associated with the data identified by the register file bypass request.

3. 发明申请

US20180095885A1 Migration of Data to Register File Cache 审中-公开
公开(公告)号：US20180095885A1
公开(公告)日：2018-04-05
申请号：US15833555
申请日：2017-12-06
申请人： MIPS Tech, LLC
发明人： Hugh Jackson , Anand Khot
IPC分类号： G06F12/0875 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0875 , G06F9/30101 , G06F9/30138 , G06F9/384 , G06F2212/45 , G06F2212/452
摘要： Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.

4. 发明授权

US09690583B2 Exploiting an architected list-use operand indication in a computer system operand resource pool 有权
公开(公告)号：US09690583B2
公开(公告)日：2017-06-27
申请号：US13251519
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30138 , G06F9/3832 , G06F9/384 , G06F9/3859
摘要： A pool of available physical registers are provided for architected registers, wherein operations are performed that activate and deactivate selected architected registers, such that the deactivated selected architected registers need not retain values, and physical registers can be deallocated to the pool, wherein deallocation of physical registers is performed after a last-use by a designated last-use instruction, wherein the last-use information is provided either by the last-use instruction or a prefix instruction, wherein reads to deallocated architecture registers return an architected default value.

5. 发明授权

US09678752B2 Scheduling apparatus and method of dynamically setting the size of a rotating register 有权
公开(公告)号：US09678752B2
公开(公告)日：2017-06-13
申请号：US14258526
申请日：2014-04-22
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Tai-Song Jin
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30123 , G06F9/30112 , G06F9/30134 , G06F9/30138 , G06F9/30189
摘要： A scheduling apparatus for dynamically setting a size of a rotating register of a local register file during runtime ids provided. The scheduling apparatus may include a determiner configured to determine whether a non-rotating register of a central register file is sufficient to schedule a program loop; a selector configured to select at least one local register file to which a needed non-rotating register is allocated in response to a determination that the non-rotating register of a central register file has a size which is sufficient to loop a program loop; a scheduler configured to schedule a non-rotating register of the at least one selected local register file.

6. 发明授权

US09658852B2 Updating of shadow registers in N:1 clock domain 有权
公开(公告)号：US09658852B2
公开(公告)日：2017-05-23
申请号：US14800136
申请日：2015-07-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas Koehler , Frank Lehnert
IPC分类号： G06F3/06 , G06F9/30
CPC分类号： G06F9/30116 , G06F9/30123 , G06F9/30138 , G06F9/3863 , G06F9/3869
摘要： A processing unit includes a first storage entity being updated at a first clock cycle (CLK1) for holding a master copy of processing unit state. The processing unit further includes at least two shadow storage entities being updated with update information of the first storage entity. A shadow storage entity running at a second clock cycle (CLK2) is slower than the first clock cycle (CLK1). The first storage entity is coupled with the shadow storage entities via an intermediate storage entity, and the intermediate storage entity provides multiple storage stages for buffering consecutive update information of the first storage entity. Selection circuitry is adapted to provide one update information contained in one storage stage to the shadow storage entity with the active clock edge of the second clock cycle (CLK2) in order to update said shadow storage entity.

7. 发明申请

US20170083324A1 GENERATION AND USE OF MEMORY ACCESS INSTRUCTION ORDER ENCODINGS 审中-公开
公开(公告)号：US20170083324A1
公开(公告)日：2017-03-23
申请号：US14921855
申请日：2015-10-23
申请人： Microsoft Technology Licensing, LLC
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.

8. 发明申请

US20170060593A1 HIERARCHICAL REGISTER FILE SYSTEM 审中-公开
标题翻译：分层寄存器文件系统
公开(公告)号：US20170060593A1
公开(公告)日：2017-03-02
申请号：US14843921
申请日：2015-09-02
申请人： QUALCOMM Incorporated
发明人： Anil KRISHNA , Rodney Wayne SMITH , Sandeep Suresh NAVADA , Shivam PRIYADARSHI , Niket Kumar CHOUDHARY , Raguram DAMODARAN
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30105 , G06F9/30138 , G06F9/384 , G06F9/3867
摘要： Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.
摘要翻译：系统和方法涉及包括1级物理寄存器文件（L1 PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。识别在处理器的指令流水线中执行的指令的生成的子集，其具有用于一个或多个未来指令的高似然性。生产的子集存储在L1 PRF中，而所有生产都存储在后备PRF中。

9. 发明授权

US09304771B2 Indirect instruction predication 有权
标题翻译：间接指令预测
公开(公告)号：US09304771B2
公开(公告)日：2016-04-05
申请号：US13766374
申请日：2013-02-13
申请人： International Business Machines Corporation
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30 , G06F9/35
CPC分类号： G06F9/30058 , G06F9/30065 , G06F9/30069 , G06F9/30072 , G06F9/30098 , G06F9/30138 , G06F9/30145 , G06F9/3016 , G06F9/30163 , G06F9/35
摘要： A method, circuit arrangement, and program product for selectively predicating instructions in an instruction stream by determining a first register address from an instruction, determining a second register address based on a value stored at the first register address, and determining whether to predicate the instruction based at least in part on a value stored at the second register address. Predication logic may analyze the instruction to determine the first register address, analyze a register corresponding to the first register address to determine the second register address, and communicate a predication signal to an execution unit based at least in part on the value stored at the second register address.
摘要翻译：一种用于通过从指令中确定第一寄存器地址来选择性地预测指令流中的指令的方法，电路装置和程序产品，基于存储在第一寄存器地址的值确定第二寄存器地址，以及确定是否对指令进行谓词至少部分地基于存储在第二寄存器地址的值。预测逻辑可以分析指令以确定第一寄存器地址，分析对应于第一寄存器地址的寄存器以确定第二寄存器地址，并且至少部分地基于存储在第二寄存器地址的值的通信给执行单元注册地址。

10. 发明授权

US09292450B2 Migration of data to register file cache 有权
标题翻译：将数据迁移到注册文件缓存
公开(公告)号：US09292450B2
公开(公告)日：2016-03-22
申请号：US14189719
申请日：2014-02-25
申请人： Imagination Technologies Limited
发明人： Hugh Jackson , Anand Khot
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F12/0875 , G06F9/30101 , G06F9/30138 , G06F9/384 , G06F2212/45 , G06F2212/452
摘要： Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit.
摘要翻译：用于无序处理器中的用于将数据迁移到与处理器的功能单元相关联的寄存器文件高速缓存以满足寄存器读取操作的方法和迁移单元。迁移单元接收对特定功能单元执行的寄存器读操作。迁移单元审查寄存器重命名表中的条目以确定特定功能单元是否最近访问了源寄存器，并且因此可能包括其寄存器文件高速缓存中的源寄存器的条目。特别地，寄存器重命名表包括用于指示哪些功能单元已访问物理寄存器的物理寄存器的条目。如果特定功能单元没有访问特定的物理寄存器，则迁移单元将数据迁移到与特定功能单元相关联的寄存器文件高速缓存。

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