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1. 发明申请

US20180234653A1 BLOCK OPERATIONS FOR AN IMAGE PROCESSOR HAVING A TWO-DIMENSIONAL EXECUTION LANE ARRAY AND A TWO-DIMENSIONAL SHIFT REGISTER 审中-公开
公开(公告)号：US20180234653A1
公开(公告)日：2018-08-16
申请号：US15946095
申请日：2018-04-05
申请人： Google LLC
发明人： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
IPC分类号： H04N5/374 , H04N5/341 , G06F5/01 , G06F17/16 , G06F12/02 , G06T1/20
CPC分类号： H04N5/3742 , G06F5/015 , G06F12/0207 , G06F17/16 , G06T1/20 , H04N5/341
摘要： A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

2. 发明申请

US20180007303A1 BLOCK OPERATIONS FOR AN IMAGE PROCESSOR HAVING A TWO-DIMENSIONAL EXECUTION LANE ARRAY AND A TWO-DIMENSIONAL SHIFT REGISTER 有权
公开(公告)号：US20180007303A1
公开(公告)日：2018-01-04
申请号：US15628527
申请日：2017-06-20
申请人： Google Inc.
发明人： Albert Meixner , Daniel Frederic Finchelstein , David Patterson , William R. Mark , Jason Rupert Redgrave , Ofer Shacham
IPC分类号： H04N5/374 , H04N5/341
CPC分类号： H04N5/3742 , G06F5/015 , G06F12/0207 , G06F17/16 , G06T1/20 , H04N5/341
摘要： A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.

3. 发明申请

US20170293467A1 APPARATUS AND METHOD FOR SUPPORTING A CONVERSION INSTRUCTION 审中-公开
公开(公告)号：US20170293467A1
公开(公告)日：2017-10-12
申请号：US15093947
申请日：2016-04-08
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS , Kelvin Domnic GOVEAS
IPC分类号： G06F5/01 , G06F9/30
CPC分类号： G06F5/015 , G06F7/483 , G06F9/30014 , G06F9/30025 , H03M7/24
摘要： A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32 performs a left shift of at least part of the input number. Selection circuitry 38 serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.

4. 发明授权

US09021000B2 High speed and low power circuit structure for barrel shifter 有权
标题翻译：桶式移位器的高速和低功耗电路结构
公开(公告)号：US09021000B2
公开(公告)日：2015-04-28
申请号：US13538001
申请日：2012-06-29
申请人： Takeo Yasuda
发明人： Takeo Yasuda
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.
摘要翻译：桶形移位器使用符号幅度2的补码转换器来产生用于其级联多路复用器选择器的解码器信号。符号输入接收移位方向，并且幅度输入接收移位量。符号幅度对2的补码转换器使用移位方向作为符号输入来计算输出结果作为移位量的2的补码，将输出结果的第一部分（最高有效位一半）分配给第一解码器信号，并且将输出结果的第二部分（最低有效位一半）到第二解码器信号。该编码方案允许解码器电路相对简单，例如用于适用于移位64位操作数值而不是常规桶形移位器所需的4比9解码器的实现的3比8解码器操作更快，面积更小，功耗更低。

5. 发明授权

US08799344B2 Comparator unit for comparing values of floating point operands 有权
标题翻译：用于比较浮点运算数值的比较器单元
公开(公告)号：US08799344B2
公开(公告)日：2014-08-05
申请号：US11394081
申请日：2006-03-31
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F7/38 , G06F9/38 , G06F7/487 , G06F9/30 , G06F7/483 , G06F7/02 , G06F7/499 , G06F5/01
CPC分类号： G06F5/012 , G06F5/015 , G06F7/026 , G06F7/483 , G06F7/4873 , G06F7/4876 , G06F7/49905 , G06F9/30014 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point comparator circuit for comparing a plurality of floating point operands includes a plurality of analysis circuits, one for each of the floating point operands, configured to determine a format of each of the floating point operands based upon floating point status information encoded within each of the floating point operands, and a result generator circuit coupled to the analysis circuits, the result generator circuit configured to generate a result signal based on the format determined by each analysis circuit and based on a comparative relationship among the floating point operands. The format of each of the floating point operands may be from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, zero, invalid operation, overflow, underflow, division by zero, exact, and inexact. The result generator circuit may ignore the encoded floating point statuses of the plurality of floating point operands when comparing just the magnitudes of the plurality of floating point operands.
摘要翻译：用于比较多个浮点操作数的浮点比较器电路包括多个分析电路，每个分析电路用于每个浮点操作数，其被配置为基于在每个浮点操作数中编码的浮点状态信息来确定每个浮点操作数的格式以及耦合到分析电路的结果生成器电路，所述结果生成器电路被配置为基于由每个分析电路确定的格式并且基于所述浮点操作数之间的比较关系生成结果信号。每个浮点操作数的格式可以来自包括以下的组：非数字（NaN），无穷大，归一化，非归一化，零，无效操作，溢出，下溢，除以零，精确和不精确。当仅比较多个浮点操作数的大小时，结果生成器电路可以忽略多个浮点操作数的编码的浮点状态。

6. 发明授权

US08793294B2 Circuit for selectively providing maximum or minimum of a pair of floating point operands 有权
公开(公告)号：US08793294B2
公开(公告)日：2014-07-29
申请号：US11394080
申请日：2006-03-31
申请人： Guy L. Steele, Jr.
发明人： Guy L. Steele, Jr.
IPC分类号： G06F7/00 , G06F7/38 , G06F7/544 , G06F9/30 , G06F9/38 , G06F7/483 , G06F7/487 , G06F5/01
CPC分类号： G06F7/4876 , G06F5/012 , G06F5/015 , G06F7/44 , G06F7/483 , G06F7/4873 , G06F7/49905 , G06F7/544 , G06F9/30021 , G06F9/30094 , G06F9/3861 , G06F9/3885
摘要： A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal, and a result assembler circuit, coupled to the decision circuit, for producing a result indicating which of the first floating point operand and the second floating point operand meet the threshold condition, based on the at least one assembly control signal. The format of the floating point operands may be from a group comprising: not-a-number (NaN), positive infinity, negative infinity, normalized, denormalized, positive overflow, negative overflow, positive underflow, negative underflow, inexact, exact, division by zero, invalid operation, positive zero, and negative zero. The result produced may be a third floating point operand having encoded floating point status information, and at least part of the encoded floating point status information in the result may come from either the first floating point operand or the second floating point operand.

7. 发明授权

US08768989B2 Funnel shifter implementation 有权
标题翻译：漏斗移位器实现
公开(公告)号：US08768989B2
公开(公告)日：2014-07-01
申请号：US13164235
申请日：2011-06-20
申请人： Raymond C. Yeung , Lincoln R. Nunes , Geoffrey F. Oh
发明人： Raymond C. Yeung , Lincoln R. Nunes , Geoffrey F. Oh
IPC分类号： G06F15/00
CPC分类号： G06F5/015
摘要： A funnel shifter includes an input, an output, and a multiplexer unit including a number of multiplexer levels. The multiplexer unit may perform one of a plurality of shift operations on an input value and to provide an output value in response to receiving a shift value and a shift operation value. A first multiplexer level may be configured to format and expand the input value into a larger intermediate value. At least a second multiplexer level may be configured to perform a linear shift of the intermediate value without wrapping any bits for creating the output value. At least some of the multiplexer levels may include multiplexer select signals that may be represented as a plurality of N-Nary one of N signals where N is greater than or equal to two, wherein each of the plurality of N-Nary signals being implemented on a set of physical wires.
摘要翻译：漏斗移位器包括输入，输出和包括多个复用器电平的多路复用器单元。复用器单元可以对输入值执行多个移位操作中的一个，并且响应于接收到移位值和移位操作值而提供输出值。可以将第一多路复用器级配置为将输入值格式化并扩展成更大的中间值。至少第二多路复用器级可以被配置为执行中间值的线性移位，而不包裹用于创建输出值的任何位。多路复用器电平中的至少一些可以包括多路复用器选择信号，其可以被表示为N个信号中的多个N个N个信号，其中N大于或等于2，其中多个N-Nary信号中的每一个被实现在一套物理线。

8. 发明申请

US20140181164A1 SELECTIVELY COMBINABLE SHIFTERS 有权
标题翻译：选择合适的切割机
公开(公告)号：US20140181164A1
公开(公告)日：2014-06-26
申请号：US14136754
申请日：2013-12-20
申请人： Wave Semiconductor, Inc.
发明人： Samit Chaudhuri
IPC分类号： G06F5/01
CPC分类号： G06F5/01 , G06F5/015
摘要： An apparatus for mathematical manipulation is described allowing the selective combination of shifters to shift binary numbers of various widths. Selective combination allows on-the-fly adjustment of shifters from independent to coordinated shifting operations. Selective combination allows adjustable hardware-based shifting while saving space and resources. Multiple eight-bit shifters can be configured for a variety of operand widths, such as a 32-bit width, a 24-bit width, a 16-bit width, or an eight-bit width. Multiplexers route the appropriate input data to the appropriate shifters. Opcodes configure the shifters for the desired type of shift and a shifted result is generated.
摘要翻译：描述了用于数学操作的装置，允许移位器的选择性组合来移动各种宽度的二进制数。选择性组合允许从独立到协调移位操作的移位器的即时调整。选择性组合允许可调整的基于硬件的移位，同时节省空间和资源。可以为多种操作数宽度配置多个8位移位器，例如32位宽度，24位宽度，16位宽度或8位宽度。多路复用器将适当的输入数据传送到适当的移位器。操作码将移位器配置为所需的移位类型，并生成移位结果。

9. 发明申请

US20140089363A1 HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER 有权
标题翻译： BARREL SHIFTER高速低功率电路结构
公开(公告)号：US20140089363A1
公开(公告)日：2014-03-27
申请号：US14094794
申请日：2013-12-03
申请人： International Business Machines Corporation
发明人： Takeo Yasuda
IPC分类号： G06F5/01
CPC分类号： G06F5/015
摘要： A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.
摘要翻译：桶形移位器使用符号幅度2的补码转换器来产生用于其级联多路复用器选择器的解码器信号。符号输入接收移位方向，并且幅度输入接收移位量。符号幅度对2的补码转换器使用移位方向作为符号输入来计算输出结果作为移位量的2的补码，将输出结果的第一部分（最高有效位一半）分配给第一解码器信号，并且将输出结果的第二部分（最低有效位一半）到第二解码器信号。使用符号幅度到2的补码转换器的编码方案允许解码器电路相对简单，例如用于64位操作数值的3比8解码器，而不是常规桶中所需的4比-9解码器移位器，导致更快的操作，更少的面积和更低的功耗。

10. 发明申请

US20140006466A1 HIGH SPEED AND LOW POWER CIRCUIT STRUCTURE FOR BARREL SHIFTER 有权
公开(公告)号：US20140006466A1
公开(公告)日：2014-01-02
申请号：US13538001
申请日：2012-06-29
申请人： Takeo Yasuda
发明人： Takeo Yasuda
IPC分类号： G06F7/00
CPC分类号： G06F5/015
摘要： A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

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