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    • 3. 发明授权
    • Automated critical area allocation in a physical synthesized hierarchical design
    • 物理合成分层设计中的自动关键区域分配
    • US08656332B2
    • 2014-02-18
    • US12394035
    • 2009-02-26
    • Bruce M. FleischerDavid J. GeigerHung C. NgoRuchir PuriHaoxing Ren
    • Bruce M. FleischerDavid J. GeigerHung C. NgoRuchir PuriHaoxing Ren
    • G06F17/50
    • G06F17/5072G06F2217/84
    • A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
    • 公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法,计算机程序产品和数据处理系统。 为了准备全局优化,在单元级别的整个单元,宏级单元被分配一个“放置力”,其用于限制宏级单元从其当前位置的移动。 还定义每个宏元素的移动边界,以便将给定宏元素中的组件保持在彼此相对接近。 然后,通过力导向布局算法,在设计的“扁平化”模型上执行单元设计的优化/放置,同时遵循移动边界。 在这种“扁平化”优化之后,放置的“单位级”单元被建模为阻塞,并且宏元素被单独地优化,同时尊重阻塞的位置。 重复这个整个过程,直到单元布局的优化最终收敛。
    • 4. 发明申请
    • Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design
    • 物理综合分层设计中的自动关键区域分配
    • US20100218155A1
    • 2010-08-26
    • US12394035
    • 2009-02-26
    • Bruce M. FleischerDavid J. GeigerHung C. NgoRuchir PuriHoaxing Ren
    • Bruce M. FleischerDavid J. GeigerHung C. NgoRuchir PuriHoaxing Ren
    • G06F17/50
    • G06F17/5072G06F2217/84
    • A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other.Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages. This entire process is repeated until the optimization of the unit layout eventually converges.
    • 公开了一种用于在分级集成电路设计中有效执行时序关键单元级单元的自动布置的方法,计算机程序产品和数据处理系统。 为了准备全局优化,在单元级别的整个单元,宏级单元被分配一个“放置力”,其用于限制宏级单元从其当前位置的移动。 还定义每个宏元素的移动边界,以便将给定宏元素中的组件保持在彼此相对接近。 然后,通过力导向布局算法,在设计的“扁平化”模型上执行单元设计的优化/放置,同时遵循移动边界。 在这种“扁平化”优化之后,放置的“单位级”单元被建模为阻塞,并且宏元素被单独地优化,同时尊重阻塞的位置。 重复这个整个过程,直到单元布局的优化最终收敛。