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1. 发明授权

US09362001B2 Memory cell capable of operating under low voltage conditions 有权
标题翻译：能够在低电压条件下运行的存储单元
公开(公告)号：US09362001B2
公开(公告)日：2016-06-07
申请号：US14798478
申请日：2015-07-14
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/18 , G11C17/16 , G11C29/00
CPC分类号： G11C17/18 , G11C16/0408 , G11C16/0433 , G11C16/08 , G11C16/10 , G11C16/14 , G11C17/16 , G11C29/785 , H01L23/5252 , H01L23/5256 , H01L27/10897 , H01L27/1116 , H01L27/11206 , H01L27/11524 , H01L27/1156 , H01L29/0649 , H01L29/1033 , H01L29/78 , H01L29/8611 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.
摘要翻译：存储单元包括编程选择晶体管，随后的栅极晶体管，反熔丝元件和读取电路。由反熔丝元件形成的充电电流可以在存储单元的读取操作期间触发读取电路形成稳定的读取电流，从而可以缩短从存储单元读取数据的时间。可以在存储单元的读取操作开始时进行放电处理，从而可以扩大从存储单元读取数据的时间窗口。

2. 发明授权

US09224497B2 One time programmable memory cell capable of reducing leakage current and preventing slow bit response 有权
标题翻译：一次可编程存储单元能够减少漏电流并防止缓慢的位响应
公开(公告)号：US09224497B2
公开(公告)日：2015-12-29
申请号：US14697652
申请日：2015-04-28
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/16 , H01L27/10 , H01L27/112 , G11C17/18 , H01L29/78 , H01L23/525
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11206 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
摘要翻译：本发明提供一种包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管的一次性可编程（OTP）存储单元。选择栅极晶体管具有分别耦合到第一漏极端子和第一源极端子的第一栅极端子，第一漏极端子，第一源极端子和两个第一源极/漏极扩展区域。以下栅极晶体管具有分别耦合到第二漏极端子和第二源极端子的两个第二源极/漏极延伸区域的第二栅极端子，第二漏极端子，耦合到第一漏极端子的第二源极端子。反熔丝变容二极管具有第三栅极端子，第三漏极端子，耦合到第二漏极端子的第三源极端子和与第三漏极端子和第三源极端子耦合的第三源极/漏极扩展区域，用于短路第三漏极端子和第三源终端。

3. 发明申请

US20170301634A1 SEMICONDUCTOR APPARATUS WITH FAKE FUNCTIONALITY 审中-公开
公开(公告)号：US20170301634A1
公开(公告)日：2017-10-19
申请号：US15387609
申请日：2016-12-21
申请人： eMemory Technology Inc.
发明人： Hsin-Ming Chen , Lun-Chun Chen , Meng-Yi Wu , Chih-Hao Huang , Tung-Cheng Kuo
IPC分类号： H01L23/00 , H01L23/522 , H01L29/06 , H01L27/088 , H01L29/78
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

4. 发明申请

US20170125121A1 ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY AND READ SENSING METHOD THEREOF 有权
公开(公告)号：US20170125121A1
公开(公告)日：2017-05-04
申请号：US15408942
申请日：2017-01-18
申请人： eMemory Technology Inc.
发明人： Yung-Jui Chen , Chih-Hao Huang
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/12 , G11C11/5692 , G11C17/16
摘要： A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit line pairs. Firstly, the plural bit line pairs are precharged to a precharge voltage. Then, a selected memory cell connected with a specific bit line pair is determined. Then, two bit lines of the specific bit line pair are respectively connected with the data line and the reference line and are discharged to a reset voltage. After a first cell current and a second cell current from the specific bit line pair are received, a first voltage level of the data line and a second voltage level of the reference line are gradually changed from the reset voltage. According to a result of comparing the first voltage level and the second voltage level, an output signal is generated.

5. 发明申请

US20140293673A1 NONVOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME 审中-公开
标题翻译：非易失性存储器单元结构及其编程和读取方法
公开(公告)号：US20140293673A1
公开(公告)日：2014-10-02
申请号：US14176162
申请日：2014-02-10
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Yueh-Chia Wen , Chin-Yi Chen , Lun-Chun Chen , Hsin-Ming Chen
IPC分类号： H01L27/112 , G11C17/16
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile memory cell structure includes a doping well disposed in a substrate, an antifuse gate disposed on the doping well, a drain disposed in the substrate, an optional select gate disposed on the doping well and an optional shallow trench isolation disposed inside the doping well.
摘要翻译：非易失性存储单元结构包括：设置在衬底中的掺杂阱，设置在掺杂阱上的反熔丝，设置在衬底中的漏极，设置在掺杂阱上的任选的选择栅极和布置在掺杂阱内部的可选的浅沟槽隔离。

6. 发明授权

US10475491B2 Random code generator with antifuse differential cell and associated sensing method 有权
公开(公告)号：US10475491B2
公开(公告)日：2019-11-12
申请号：US15958460
申请日：2018-04-20
申请人： eMemory Technology Inc.
发明人： Yung-Jui Chen , Chih-Hao Huang
IPC分类号： G11C17/16 , G11C7/22 , H01L27/06 , H01L27/112 , G06F21/73 , G11C7/06 , G11C7/12 , G11C7/24 , G11C17/18 , G11C16/34 , G11C29/44 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C11/56 , G11C16/04 , H02H9/04 , G06F7/00 , H04L9/08 , G11C16/06 , G11C16/10 , G11C16/14
摘要： A random code generator includes a memory cell array and a sensing circuit. The memory cell array includes plural antifuse differential cells. The sensing circuit has an input terminal and an inverted input terminal. When a first antifuse differential cell of the memory cell array is a selected cell, a bit line of the selected cell is connected with the input terminal of the sensing circuit and an inverted bit line of the selected cell is connected with the inverted input terminal of the sensing circuit. During a read cycle, the sensing circuit judges a storage state of the selected cell according to a first charging current of the bit line and a second charging current of the inverted bit line, and determines a bit of a random code according to the storage state of the selected cell.

7. 发明授权

US09627088B2 One time programmable non-volatile memory and read sensing method thereof 有权
公开(公告)号：US09627088B2
公开(公告)日：2017-04-18
申请号：US14630766
申请日：2015-02-25
申请人： eMemory Technology Inc.
发明人： Yung-Jui Chen , Chih-Hao Huang
IPC分类号： G11C17/18 , G11C17/16 , G11C7/06 , G11C7/08 , G11C7/12
CPC分类号： G11C17/18 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/12 , G11C11/5692 , G11C17/16
摘要： A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

8. 发明申请

US20160247580A1 ONE TIME PROGRAMMABLE NON-VOLATILE MEMORY AND READ SENSING METHOD THEREOF 有权
标题翻译：一次性可编程非易失性存储器和读取传感方法
公开(公告)号：US20160247580A1
公开(公告)日：2016-08-25
申请号：US14630766
申请日：2015-02-25
申请人： eMemory Technology Inc.
发明人： Yung-Jui Chen , Chih-Hao Huang
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18 , G11C7/062 , G11C7/067 , G11C7/08 , G11C7/12 , G11C11/5692 , G11C17/16
摘要： A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.
摘要翻译：提供了一种用于OTP非易失性存储器的读取感测方法。存储器阵列与多个位线连接。读取感测方法包括以下步骤。首先，将多个位线预充电为预充电电压。然后，确定存储器阵列的所选择的存储单元，其中所选择的存储单元与多个位线的第一位线连接。然后，与选择的存储单元相对应的位线与数据线连接，数据线被放电到复位电压。在接收到来自所选存储单元的单元电流之后，数据线的电压电平从复位电压逐渐变化。根据将数据线的电压电平与比较电压进行比较的结果，产生输出信号。

9. 发明申请

US20160012894A1 NON-VOLATILE MEMORY AND COLUMN DECODER THEREOF 有权
标题翻译：非易失性存储器及其解码器
公开(公告)号：US20160012894A1
公开(公告)日：2016-01-14
申请号：US14592477
申请日：2015-01-08
申请人： eMemory Technology Inc.
发明人： Tzu-Neng Lai , Chih-Hao Huang
IPC分类号： G11C16/08 , G11C16/26 , G11C16/10
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A non-volatile memory includes a memory array, a row decoder, a column decoder, a write buffer and a sensing circuit. The column decoder includes a programming decoder and a reading decoder. The programming decoder is connected with n bit lines of the memory array. The reading decoder is connected with the n bit lines. During a program cycle, a programming control signal set is activated. Consequently, the programming decoder determines a selected memory cell, and a cell current generated by the selected memory cell flows to the write buffer through the programming decoder and a programming data line. During a read cycle, a reading control signal set is activated. Consequently, the reading decoder determines the selected memory cell, and the cell current generated by the selected memory cell flows to the sensing circuit through the reading decoder and a reading data line.
摘要翻译：非易失性存储器包括存储器阵列，行解码器，列解码器，写缓冲器和感测电路。列解码器包括编程解码器和读取解码器。编程解码器与存储器阵列的n位线连接。读取解码器与n位线连接。在编程周期中，编程控制信号组被激活。因此，编程解码器确定所选择的存储单元，并且由所选择的存储器单元产生的单元电流通过编程解码器和编程数据线流向写入缓冲器。在读取周期期间，读取控制信号组被激活。因此，读取解码器确定所选择的存储单元，并且由选择的存储单元产生的单元电流通过读取解码器和读取数据线流到感测电路。

10. 发明申请

US20150243366A1 ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME 有权
标题翻译：一个可编程存储器单元和用于编程和读取包含该存储器单元的存储器阵列的方法
公开(公告)号：US20150243366A1
公开(公告)日：2015-08-27
申请号：US14697652
申请日：2015-04-28
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/16 , H01L27/112 , H01L29/78 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11206 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
摘要翻译：本发明提供一种包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管的一次性可编程（OTP）存储单元。选择栅极晶体管具有分别耦合到第一漏极端子和第一源极端子的第一栅极端子，第一漏极端子，第一源极端子和两个第一源极/漏极扩展区域。以下栅极晶体管具有分别耦合到第二漏极端子和第二源极端子的两个第二源极/漏极延伸区域的第二栅极端子，第二漏极端子，耦合到第一漏极端子的第二源极端子。反熔丝变容二极管具有第三栅极端子，第三漏极端子，耦合到第二漏极端子的第三源极端子和与第三漏极端子和第三源极端子耦合的第三源极/漏极扩展区域，用于短路第三漏极端子和第三源终端。

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