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1. 发明授权

US09760301B2 WOM code emulation of EEPROM-type devices 有权
公开(公告)号：US09760301B2
公开(公告)日：2017-09-12
申请号：US14826183
申请日：2015-08-13
申请人： Texas Instruments Incorporated
发明人： Yuming Zhu , Manish Goel , Clive Bittlestone
IPC分类号： G06F12/00 , G11C17/00 , G06F3/06 , G11C17/14 , G06F9/445 , G06F12/02 , G06F17/30
CPC分类号： G06F3/0634 , G06F3/0614 , G06F3/0616 , G06F3/0685 , G06F8/66 , G06F12/0246 , G06F17/30188 , G06F2206/1014 , G11C17/146
摘要： A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

2. 发明授权

US09640262B2 Highly scalable single-poly non-volatile memory cell 有权
公开(公告)号：US09640262B2
公开(公告)日：2017-05-02
申请号：US14719342
申请日：2015-05-22
申请人： eMemory Technology Inc.
发明人： Te-Hsun Hsu , Chun-Hsiao Li , Hsuen-Wei Chen
IPC分类号： H01L29/788 , G11C16/08 , G11C17/16 , G11C17/18 , H01L27/112 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , H01L23/528 , H01L27/06 , H01L29/10 , H01L29/49 , H01L29/93 , H01L27/11524 , H03K3/356 , G11C17/14 , G11C29/00 , H01L23/525
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

3. 发明申请

US20170046090A1 WOM CODE EMULATION OF EEPROM-TYPE DEVICES 有权
标题翻译： EEPROM类型器件的代码仿真
公开(公告)号：US20170046090A1
公开(公告)日：2017-02-16
申请号：US14826183
申请日：2015-08-13
申请人： Texas Instruments Incorporated
发明人： Yuming Zhu , Manish Goel , Clive Bittlestone
IPC分类号： G06F3/06 , G06F9/455
CPC分类号： G06F3/0634 , G06F3/0614 , G06F3/0616 , G06F3/0685 , G06F8/66 , G06F12/0246 , G06F17/30188 , G06F2206/1014 , G11C17/146
摘要： A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.
摘要翻译：用于EEPROM型设备的一次写入存储器（WOM）代码仿真的系统包括例如用于发送存储在WOM（只写存储器）设备中的数据字的主机处理器。主机接口由WOM控制器接收用于编码的数据字。模拟器将WOM编码数据和地址标识符编程为WOM设备的条目。仿真器通过搜索WOM设备的当前活动页面的条目来覆盖先前编程的WOM编码数据，以定位包括搜索到的地址标识符和先前写入的WOM编码数据字的编程的WOM条目。当先前写入的WOM编码字不能被正确覆盖时，第二WOM编码字的内容被存储在一个新条目中。当当前活动页面基本上已满时，新条目被存储在新页面中，并且当前活动页面被块擦除。

4. 发明授权

US09355740B2 Semiconductor nonvolatile memory device with one-time programmable memories 有权
标题翻译：具有一次可编程存储器的半导体非易失性存储器件
公开(公告)号：US09355740B2
公开(公告)日：2016-05-31
申请号：US14491074
申请日：2014-09-19
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Koichiro Zaitsu , Kosuke Tatsumura
IPC分类号： G11C16/04 , G11C17/18 , G11C5/06 , G11C17/14
CPC分类号： G11C17/18 , G11C5/063 , G11C17/146
摘要： A semiconductor nonvolatile memory device of an embodiment includes: a plurality of transistors arranged in a matrix, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write unit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation.
摘要翻译：实施例的半导体非易失性存储器件包括：以矩阵形式布置的多个晶体管，同一行中的晶体管串联连接以形成具有第一端子和第二端子的晶体管串; 多个第一布线，每一个对应于一列之一，并连接到相应列的晶体管的栅极; 连接到其中设置每个晶体管的每个半导体区域的公共第一电极; 以及写入单元，其选择所述第一布线和所述晶体管串中的一个，并将第一电压施加到所述第一电极，对所选择的第一布线施加第一写入电压，向所述其它第一布线施加第二电压，以及在写入操作中第二写入电压到所选择的晶体管串的第一端子和第二端子。

5. 发明申请

US20160013776A1 LEVEL SHIFT DRIVER CIRCUIT CAPABLE OF REDUCING GATE-INDUCED DRAIN LEAKAGE CURRENT 有权
标题翻译：降低闸门感应漏水电流的水平移位驱动电路
公开(公告)号：US20160013776A1
公开(公告)日：2016-01-14
申请号：US14711765
申请日：2015-05-13
申请人： eMemory Technology Inc.
发明人： Po-Hao Huang
IPC分类号： H03K3/356
CPC分类号： G11C16/08 , G11C16/10 , G11C16/26 , G11C17/04 , G11C17/08 , G11C17/146 , G11C17/16 , G11C17/18 , G11C29/76 , H01L23/5252 , H01L23/528 , H01L27/0629 , H01L27/11206 , H01L27/11524 , H01L29/1079 , H01L29/4916 , H01L29/93 , H01L2924/0002 , H03K3/356182 , H01L2924/00
摘要： A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.
摘要翻译：电平移位驱动器电路包括电平移位电路和驱动器电路。驱动器电路包括第一和第二P型晶体管和串联耦合的第一和第二N型晶体管。当电平移位电路的第一输入信号处于工作电压时，电平移位电路关断第二N型晶体管。第一N型晶体管的控制端子接收工作电压，以避免第二N型晶体管的栅极引起的漏极漏电流。当第一输入信号处于系统基极电压时，电平移位电路关断第一P型晶体管。第二P型晶体管的控制端子接收工作电压以避免第一P型晶体管的栅极引起的漏极漏电流。

6. 发明申请

US20150310927A1 LOW-PIN-COUNT NON-VOLATILE MEMORY INTERFACE WITH SOFT PROGRAMMING CAPABILITY 有权
标题翻译：具有软编程能力的低引号计数非易失性存储器接口
公开(公告)号：US20150310927A1
公开(公告)日：2015-10-29
申请号：US14792479
申请日：2015-07-06
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/18 , G11C17/16 , G11C13/00 , G11C16/04
CPC分类号： G11C17/18 , G11C7/10 , G11C8/18 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/0408 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C17/00 , G11C17/146 , G11C17/16 , G11C29/022 , G11C29/027 , G11C29/1201 , G11C29/46 , G11C2216/30
摘要： A low-pin-count non-volatile (NVM) memory with no more than two control signals that can at least program NVM cells, load data to be programmed into output registers, or read the NVM cells. At least one of the NVM cells has at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector is coupled to a second supply voltage line and having a select signal. No more than two control signals can be used to select the at least one NVM cells in the NVM sequentially for programming the data into the at least one NVM cells or loading data into the at least one output registers. Programming into the NVM cells, or loading data into output registers, can be determined by the voltage levels of the first to the second supply voltage lines.
摘要翻译：具有不超过两个控制信号的低引脚数非易失性（NVM）存储器，可以至少编程NVM单元，将要编程的数据加载到输出寄存器中，或读取NVM单元。至少一个NVM单元具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。选择器耦合到第二电源电压线并且具有选择信号。可以使用不超过两个控制信号来选择NVM中的至少一个NVM单元，以将数据编程到至少一个NVM单元中或将数据加载到至少一个输出寄存器中。可以通过第一至第二电源电压线的电压电平来确定对NVM单元的编程或将数据加载到输出寄存器中。

7. 发明授权

US09165631B2 OTP scheme with multiple magnetic tunnel junction devices in a cell 有权
标题翻译： OTP方案在单元中具有多个磁性隧道结装置
公开(公告)号：US09165631B2
公开(公告)日：2015-10-20
申请号：US13613125
申请日：2012-09-13
申请人： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Kangho Lee
发明人： Jung Pill Kim , Taehyun Kim , Sungryul Kim , Kangho Lee
IPC分类号： G11C11/16 , G11C17/00 , G11C17/02 , G11C17/16 , G11C17/14
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1673 , G11C17/02 , G11C17/146 , G11C17/165 , G11C2213/78
摘要： A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of the multiple MTJs in a unit cell can be coupled to separate programming circuitry and/or separate sense amplifier circuitry so that they can be individually programmed and/or individually sensed. A logical combination from the separate sense amplifiers can be generated as an output of the unit cell.
摘要翻译：一次编程（OTP）装置单元包括多个磁隧道结（MTJ）和耦合在多个MTJ之间的共享存取晶体管和固定电位。单位单元中的多个MTJ中的每一个可以耦合到单独的编程电路和/或单独的读出放大器电路，使得它们可以被单独编程和/或单独感测。可以产生来自单独读出放大器的逻辑组合作为单位单元的输出。

8. 发明授权

US08923085B2 Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access 有权
标题翻译：嵌入集成电路中的低引脚数非易失性存储器，无需任何附加引脚进行访问
公开(公告)号：US08923085B2
公开(公告)日：2014-12-30
申请号：US14231413
申请日：2014-03-31
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/18 , G11C7/10 , G11C17/00 , G11C16/10 , G11C29/02 , G11C8/18 , G11C16/16 , G11C16/26 , G11C16/32
CPC分类号： G11C17/18 , G11C7/10 , G11C8/18 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/0408 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C17/00 , G11C17/146 , G11C17/16 , G11C29/022 , G11C29/027 , G11C29/1201 , G11C29/46 , G11C2216/30
摘要： A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.
摘要翻译：可以访问嵌入集成电路的低引脚数非易失性存储器（NVM），无需任何额外的引脚。 NVM具有一个或多个存储器单元，并且至少一个NVM单元可以具有耦合到至少一个选择器和第一电源电压线的至少一个NVM元件。选择器可以耦合到第二电源电压线并且具有选择信号。集成电路可以包括至少一个测试模式检测电路，用于在检测到异常（或正常））操作条件时激活测试模式。一旦测试模式被激活，集成电路的至少一个I / O或电源电压可以用作NVM的I / O或电源电压，以选择至少一个NVM单元进行读取，编程为非易失性或易失性州。在至少一个电源电压线的斜坡期间可以读取至少一个NVM单元。

9. 发明申请

US20140223078A1 VIRTUAL OTP PRE-PROGRAMMING 有权
标题翻译：虚拟OTP预编程
公开(公告)号：US20140223078A1
公开(公告)日：2014-08-07
申请号：US13931015
申请日：2013-06-28
申请人： Broadcom Corporation
发明人： Charles Joseph Gravelle
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F12/0246 , G11C16/102 , G11C17/146
摘要： Aspects of virtual one-time programmable (OTP) memory pre-programming are described. A device may include a logical sink destination, an OTP memory map, a virtual memory map, and a comparator. The OTP memory map may store one or more OTP logical values, and the virtual memory map may store one or more default virtual logical values. Generally, the virtual memory map may be predefined for various representative OTP scenarios including test and customer-specific values. Certain portions or outputs of the logical values stored in the OTP memory map and the virtual memory map may be compared by the comparator, and the logical result of the comparison may be output to the logical sink destination. In certain aspects, the portions or outputs of OTP and virtual memory maps that are compared may be determined based on various factors such as strap option settings, temperatures, voltages, or register values of the device.
摘要翻译：描述虚拟一次可编程（OTP）存储器预编程的方面。设备可以包括逻辑宿目的地，OTP存储器映射，虚拟存储器映射和比较器。 OTP存储器映射可以存储一个或多个OTP逻辑值，并且虚拟存储器映射可以存储一个或多个默认虚拟逻辑值。通常，虚拟存储器映射可以针对各种代表性的OTP场景预定义，包括测试和客户特定的值。存储在OTP存储器映射图和虚拟存储器映射中的逻辑值的某些部分或输出可以由比较器进行比较，并且比较的逻辑结果可被输出到逻辑存储器目的地。在某些方面，可以基于诸如条带选项设置，温度，电压或设备的寄存器值的各种因素来确定被比较的OTP和虚拟存储器映射的部分或输出。

10. 发明申请

US20140029362A1 MECHANISMS FOR BULIT-IN SELF TEST AND REPAIR FOR MEMORY DEVICES 有权
标题翻译：用于自动测试和修理内存设备的机制
公开(公告)号：US20140029362A1
公开(公告)日：2014-01-30
申请号：US13560571
申请日：2012-07-27
申请人： Saman ADHAM , Chao-Jung HUNG
发明人： Saman ADHAM , Chao-Jung HUNG
IPC分类号： G11C29/04
CPC分类号： G11C29/4401 , G11C17/146 , G11C17/16 , G11C29/785 , G11C2029/4402
摘要： This description relates to a system for storing repair data of a random access memory (RAM) array in a one-time programming memory (OTPM). The system includes the RAM array, wherein the RAM array includes a main memory, redundant rows and columns, and a first repair register memory. The system further includes a built-in self-test-and-repair (BISTR) module having a second repair register memory, wherein the BISTR module is used to test and repair the RAM array. The system further includes the one-time programming memory (OTPM) for storing repair data from more than one test and repair stages for the RAM array, wherein the repair data from different test and repair stages are stored in a same data segment.
摘要翻译：该描述涉及用于存储随机存取存储器（RAM）阵列在一次性编程存储器（OTPM）中的修复数据的系统。该系统包括RAM阵列，其中RAM阵列包括主存储器，冗余行和列以及第一修复寄存器存储器。该系统还包括具有第二修复寄存器存储器的内置自检和修复（BISTR）模块，其中BISTR模块用于测试和修复RAM阵列。该系统还包括用于存储来自RAM阵列的多于一个测试和修复阶段的修复数据的一次性编程存储器（OTPM），其中来自不同测试和修复阶段的修复数据被存储在相同的数据段中。

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