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1. 发明申请

US20180151584A1 COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING IN A DIELECTRIC INTERFACE 审中-公开
公开(公告)号：US20180151584A1
公开(公告)日：2018-05-31
申请号：US15810979
申请日：2017-11-13
申请人： STMicrielectronics (Rousset) SAS
发明人： Francesco La Rosa , Stephan Niel , Arnaud Regnier
IPC分类号： H01L27/11563 , H01L27/11536
CPC分类号： H01L27/11563 , G11C16/0433 , G11C16/0466 , H01L27/11536 , H01L27/1157 , H01L29/40117 , H01L29/42352
摘要： Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.

2. 发明授权

US09882033B2 Method of manufacturing a non-volatile memory cell and array having a trapping charge layer in a trench 有权
公开(公告)号：US09882033B2
公开(公告)日：2018-01-30
申请号：US15368451
申请日：2016-12-02
申请人： Silicon Storage Technology, Inc.
发明人： Nhan Do
IPC分类号： G11C11/34 , H01L29/792 , H01L21/3205 , H01L29/788 , H01L29/66 , H01L27/11565 , H01L27/11568 , H01L29/423 , H01L21/02
CPC分类号： H01L29/66833 , H01L21/0217 , H01L27/1052 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/7926
摘要： A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.

3. 发明申请

US20170301682A1 ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20170301682A1
公开(公告)日：2017-10-19
申请号：US15481889
申请日：2017-04-07
申请人： eMemory Technology Inc.
发明人： Chun-Hsiao Li , Wei-Ren Chen , Hsueh-Wei Chen
IPC分类号： H01L27/115 , H01L29/423 , H01L29/78 , G11C16/14
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/10 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

4. 发明授权

US09754816B2 Semiconductor device and method of manufacturing semiconductor device 有权
公开(公告)号：US09754816B2
公开(公告)日：2017-09-05
申请号：US15087427
申请日：2016-03-31
申请人： Renesas Electronics Corporation
发明人： Yoshihiro Hayashi , Naoya Inoue , Kishou Kaneko
IPC分类号： H01L21/44 , H01L21/768 , H01L21/28 , H01L27/12 , H01L29/423 , H01L29/792 , H01L29/41 , H01L29/49 , H01L29/51 , H01L29/786 , H01L29/66 , H01L29/24
CPC分类号： H01L21/76807 , H01L21/28282 , H01L21/76877 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/242 , H01L29/41 , H01L29/42344 , H01L29/42352 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/518 , H01L29/66757 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/792
摘要： The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.

5. 发明授权

US09595612B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09595612B2
公开(公告)日：2017-03-14
申请号：US15006522
申请日：2016-01-26
申请人： Samsung Electronics Co., Ltd.
发明人： Jung-Hwan Kim , Hun-Hyeoung Leam , Tae-Hyun Kim , Seok-Woo Nam , Hyun Namkoong , Yong-Seok Kim , Tea-Kwang Yu
IPC分类号： H01L29/76 , H01L29/78 , H01L21/28 , H01L21/762 , H01L21/8234 , H01L27/115 , H01L29/423 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/785 , H01L21/28282 , H01L21/308 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/0649 , H01L29/0653 , H01L29/0657 , H01L29/1079 , H01L29/42352 , H01L29/66818 , H01L29/66833 , H01L29/7851 , H01L29/7854 , H01L2029/7858
摘要： A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
摘要翻译：半导体器件包括限定形成在半导体衬底中的有源区的隔离层。在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。执行第一舍入处理以围绕活动区域的边缘部分。在隔离层上进行第二凹陷处理。执行第二舍入处理以围绕活动区域的边缘部分。

6. 发明授权

US09548380B2 Non-volatile memory cell having a trapping charge layer in a trench and an array and a method of manufacturing therefor 有权
标题翻译：在沟槽中具有捕获电荷层的阵列的非易失性存储单元及其制造方法
公开(公告)号：US09548380B2
公开(公告)日：2017-01-17
申请号：US13829111
申请日：2013-03-14
申请人： Silicon Storage Technology, Inc.
发明人： Nhan Do
IPC分类号： G11C11/34 , H01L29/792 , H01L21/3205 , H01L29/788 , H01L29/66 , H01L27/105 , H01L29/423 , H01L27/115
CPC分类号： H01L29/66833 , H01L21/0217 , H01L27/1052 , H01L27/11565 , H01L27/11568 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/7926
摘要： A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.
摘要翻译：通过在衬底表面形成沟槽形成的存储单元。第一和第二间隔开的区域形成在衬底中，其间具有通道区域。第一区域形成在沟槽下方。沟道区域包括沿着沟槽的侧壁延伸的第一部分和沿衬底的表面延伸的第二部分。沟槽中的电荷捕获层与沟道区的第一部分相邻并与其绝缘，用于控制沟道区第一部分的导通。沟槽中的导电栅极与电荷俘获层相邻并且与第一区绝缘，并与电荷捕获层电容耦合。导电控制栅极设置在沟道区域的第二部分上并与沟道区域的第二部分绝缘，用于控制其导通。

7. 发明授权

US09515081B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09515081B2
公开(公告)日：2016-12-06
申请号：US14628939
申请日：2015-02-23
申请人： Cypress Semiconductor Corporation
发明人： Yukio Hayakawa , Yukihiro Utsuno
IPC分类号： H01L29/792 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/51 , H01L21/02 , H01L21/311 , H01L21/768 , H01L23/528
CPC分类号： H01L27/11568 , H01L21/02164 , H01L21/0217 , H01L21/0223 , H01L21/28282 , H01L21/31111 , H01L21/31144 , H01L21/768 , H01L23/528 , H01L27/115 , H01L29/42352 , H01L29/511 , H01L29/513 , H01L29/518 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.
摘要翻译：半导体器件包括设置在半导体衬底中的位线; 所述ONO膜沿着所述半导体基板的表面设置并且由隧道氧化膜，捕获层和顶部氧化物膜制成; 以及氧化膜，其设置在位线之间的中间的半导体衬底的表面上并与ONO膜的侧面接触，其中氧化物膜的膜厚大于厚度的总和隧道氧化膜和顶部氧化膜，并且小于ONO膜的厚度。

8. 发明申请

US20160268302A1 SEMICONDUCTOR DEVICES INCLUDING GATE INSULATION LAYERS ON CHANNEL MATERIALS AND METHODS OF FORMING THE SAME 有权
标题翻译：在通道材料上包括门绝缘层的半导体器件及其形成方法
公开(公告)号：US20160268302A1
公开(公告)日：2016-09-15
申请号：US14995845
申请日：2016-01-14
申请人： Jung-Hwan Lee , Jee-Yong Kim , Dae-Seok Byeon
发明人： Jung-Hwan Lee , Jee-Yong Kim , Dae-Seok Byeon
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11565 , H01L27/1157 , H01L29/42352 , H01L29/66833
摘要： Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括交替绝缘层和栅电极的叠层。半导体器件包括在堆叠中的通道凹槽中的沟道材料。半导体器件在通道凹槽中包括在沟道材料上的电荷存储结构。此外，半导体器件在沟道材料上包括栅极绝缘层。栅极绝缘层将沟道材料的一部分切下。还提供了形成半导体器件的相关方法。

9. 发明授权

US09401435B2 Reconfigurable electronic devices and operation method thereof 有权
标题翻译：可重构电子设备及其操作方法
公开(公告)号：US09401435B2
公开(公告)日：2016-07-26
申请号：US14828750
申请日：2015-08-18
申请人： SNU R&DB FOUNDATION
发明人： Jong-Ho Lee
IPC分类号： G11C16/12 , H01L29/792 , H01L29/78 , H01L29/423 , G11C16/14 , G11C16/04
CPC分类号： H01L29/792 , G11C16/0466 , G11C16/12 , G11C16/14 , H01L29/4234 , H01L29/42344 , H01L29/42348 , H01L29/42352 , H01L29/78391 , H01L29/7881
摘要： Provided is a reconfigurable electronic device which is implemented by forming independent upper gates and lower gates, wherein in comparison with an existing reconfigurable electronic device having the same function, a degree of integration is greatly increased, a non-volatile memory function is included in the device, and in operation of a reconfigurable circuit based on an independent lower electrode array, dynamic parasitic component is decreased and a complexity of wire lines can be reduced, so that power consumption can be reduced. In addition, in comparison with an existing reconfigurable electronic device, the device exhibits remarkably excellent performance in terms of various characteristics such as diversity of functions of a multi-functional device, alignment margin in process, performance of implementation of infinitesimal electrical doping in a channel, compatibility with bottom-up and top-down method in process, and compatibility with a 1D or 2D material.
摘要翻译：提供了一种可重新配置的电子设备，其通过形成独立的上部门和下部门来实现，其中与具有相同功能的现有可重新配置的电子设备相比，大大增加了集成度，非易失性存储器功能被包括在器件，并且在基于独立的下电极阵列的可重构电路的操作中，动态寄生分量减小，并且可以减少有线线路的复杂性，从而可以降低功耗。此外，与现有的可重新配置的电子设备相比，该设备在多功能设备的功能多样性，处理中的对准余量，通道中的无穷小电掺杂的性能等各种特性方面表现出非常优异的性能，与自下而上和自上而下的方法在过程中的兼容性，以及与1D或2D材料的兼容性。

10. 发明授权

US09312394B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09312394B2
公开(公告)日：2016-04-12
申请号：US14744261
申请日：2015-06-19
申请人： Renesas Electronics Corporation
发明人： Yoshihiro Hayashi , Naoya Inoue , Kishou Kaneko
IPC分类号： H01L29/10 , H01L29/786 , H01L21/28 , H01L27/12 , H01L29/423 , H01L29/792 , H01L29/41 , H01L29/24 , H01L29/49 , H01L29/51
CPC分类号： H01L21/76807 , H01L21/28282 , H01L21/76877 , H01L27/1225 , H01L27/124 , H01L29/24 , H01L29/242 , H01L29/41 , H01L29/42344 , H01L29/42352 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/518 , H01L29/66757 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/792
摘要： A semiconductor device including a semiconductor substrate, a first insulating layer formed over said semiconductor substrate, first grooves formed in said first insulating layer, a gate electrode and a first interconnect filled in said first grooves, respectively, a gate insulating film formed over said gate electrode, a semiconductor layer formed over said gate insulating, a second insulating layer formed over said semiconductor layer and said first insulating film, a via formed in said second insulating layer and connected to said semiconductor layer, a second groove formed in said second insulating layer, and a second interconnect filled in said second groove, formed over said via and connected to said via.
摘要翻译：一种半导体器件，包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，分别形成在所述第一绝缘层中的第一沟槽，栅电极和填充在所述第一沟槽中的第一互连，栅极绝缘膜分别形成在所述栅极电极，形成在所述栅极绝缘上的半导体层，形成在所述半导体层和所述第一绝缘膜上的第二绝缘层，形成在所述第二绝缘层中并连接到所述半导体层的通孔，形成在所述第二绝缘层中的第二沟槽以及填充在所述第二凹槽中的第二互连件，形成在所述通孔上并连接到所述通孔。

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