专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10090260B2 Semiconductor apparatus with fake functionality 有权
公开(公告)号：US10090260B2
公开(公告)日：2018-10-02
申请号：US15387609
申请日：2016-12-21
申请人： eMemory Technology Inc.
发明人： Hsin-Ming Chen , Lun-Chun Chen , Meng-Yi Wu , Chih-Hao Huang , Tung-Cheng Kuo
IPC分类号： H01L23/00 , H01L23/522 , H01L27/088 , H01L29/06 , G11C16/14 , H01L27/11507 , H01L27/11529 , H01L29/423 , G06F7/58 , G11C17/16 , G11C17/18 , G11C16/04 , H01L27/11558 , H01L49/02 , H01L29/78
摘要： A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

2. 发明授权

US11735266B2 Antifuse-type one time programming memory cell and cell array structure with same 有权
公开(公告)号：US11735266B2
公开(公告)日：2023-08-22
申请号：US17536414
申请日：2021-11-29
申请人： eMemory Technology Inc.
发明人： Lun-Chun Chen , Jiun-Ren Chen , Ping-Lung Ho , Hsin-Ming Chen
IPC分类号： G11C16/26 , G11C16/10 , G11C16/04 , G11C16/24 , G11C16/30 , G11C17/08
CPC分类号： G11C16/102 , G11C16/0433 , G11C16/24 , G11C16/26 , G11C16/30 , G11C17/08
摘要： An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

3. 发明申请

US20200020707A1 SEMICONDUCTOR PROCESSING METHOD FOR MANUFACTURING ANTIFUSE STRUCTURE WITH IMPROVED IMMUNITY AGAINST ERRONEOUS PROGRAMMING 审中-公开
公开(公告)号：US20200020707A1
公开(公告)日：2020-01-16
申请号：US16427313
申请日：2019-05-30
申请人： eMemory Technology Inc.
发明人： Chao-Kan Yang , Lun-Chun Chen
IPC分类号： H01L27/112 , G11C17/16
摘要： A semiconductor processing method is used for manufacturing an antifuse structure. The semiconductor processing method may include using a first mask for exposing a first well region of a semiconductor substrate, performing a first Boron implantation operation to implant Boron into the first well region, using a second mask for exposing the first well region and the second well region of the semiconductor substrate, and performing a second Boron implantation operation to implant Boron into the first well region and the second well region.

4. 发明申请

US20140098591A1 ANTIFUSE OTP MEMORY CELL WITH PERFORMANCE IMPROVEMENT PREVENTION AND OPERATING METHOD OF MEMORY 有权
标题翻译：具有性能改进的防毒OTP存储器单元内存的预防和操作方法
公开(公告)号：US20140098591A1
公开(公告)日：2014-04-10
申请号：US14101367
申请日：2013-12-10
申请人： eMemory Technology Inc.
发明人： Chin-Yi Chen , Lun-Chun Chen , Yueh-Chia Wen , Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.
摘要翻译：提供了包括第一反熔丝单元，第二反熔丝单元，选择晶体管和阱区的OTP存储单元。第一和第二反熔丝单元分别包括依次设置在基板上的反熔丝层和反熔丝。选择晶体管包括选择栅极，栅极电介质层，第一掺杂区域和第二掺杂区域。选择栅极设置在基板上。栅介质层设置在选择栅极和衬底之间。第一掺杂区域和第二掺杂区域分别设置在选择栅极两侧的衬底中，其中第二掺杂区域设置在第一和第二反熔丝单元的周边处的衬底中。阱区设置在第一和第二反熔丝单元下方的衬底中，并连接到第二掺杂区。

5. 发明申请

US20170301634A1 SEMICONDUCTOR APPARATUS WITH FAKE FUNCTIONALITY 审中-公开
公开(公告)号：US20170301634A1
公开(公告)日：2017-10-19
申请号：US15387609
申请日：2016-12-21
申请人： eMemory Technology Inc.
发明人： Hsin-Ming Chen , Lun-Chun Chen , Meng-Yi Wu , Chih-Hao Huang , Tung-Cheng Kuo
IPC分类号： H01L23/00 , H01L23/522 , H01L29/06 , H01L27/088 , H01L29/78
CPC分类号： H01L23/573 , G06F7/588 , G11C16/0441 , G11C16/14 , G11C17/16 , G11C17/18 , G11C2216/10 , H01L23/5226 , H01L27/0883 , H01L27/11507 , H01L27/11529 , H01L27/11558 , H01L28/00 , H01L29/0653 , H01L29/42328 , H01L29/42344 , H01L29/42352 , H01L29/7831 , H01L29/7833 , H01L29/7841
摘要： A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

6. 发明授权

US09013910B2 Antifuse OTP memory cell with performance improvement prevention and operating method of memory 有权
标题翻译：防毒OTP存储单元具有性能提升预防和操作方法的内存
公开(公告)号：US09013910B2
公开(公告)日：2015-04-21
申请号：US14101367
申请日：2013-12-10
申请人： eMemory Technology Inc.
发明人： Chin-Yi Chen , Lun-Chun Chen , Yueh-Chia Wen , Meng-Yi Wu , Hsin-Ming Chen
IPC分类号： G11C17/00 , G11C17/16 , H01L27/112 , G11C17/18 , H01L23/525
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.
摘要翻译：提供了包括第一反熔丝单元，第二反熔丝单元，选择晶体管和阱区的OTP存储单元。第一和第二反熔丝单元分别包括依次设置在基板上的反熔丝层和反熔丝。选择晶体管包括选择栅极，栅极电介质层，第一掺杂区域和第二掺杂区域。选择栅极设置在基板上。栅介质层设置在选择栅极和衬底之间。第一掺杂区域和第二掺杂区域分别设置在选择栅极两侧的衬底中，其中第二掺杂区域设置在第一和第二反熔丝单元的周边处的衬底中。阱区设置在第一和第二反熔丝单元下方的衬底中，并连接到第二掺杂区。

7. 发明申请

US20140293673A1 NONVOLATILE MEMORY CELL STRUCTURE AND METHOD FOR PROGRAMMING AND READING THE SAME 审中-公开
标题翻译：非易失性存储器单元结构及其编程和读取方法
公开(公告)号：US20140293673A1
公开(公告)日：2014-10-02
申请号：US14176162
申请日：2014-02-10
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Yueh-Chia Wen , Chin-Yi Chen , Lun-Chun Chen , Hsin-Ming Chen
IPC分类号： H01L27/112 , G11C17/16
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile memory cell structure includes a doping well disposed in a substrate, an antifuse gate disposed on the doping well, a drain disposed in the substrate, an optional select gate disposed on the doping well and an optional shallow trench isolation disposed inside the doping well.
摘要翻译：非易失性存储单元结构包括：设置在衬底中的掺杂阱，设置在掺杂阱上的反熔丝，设置在衬底中的漏极，设置在掺杂阱上的任选的选择栅极和布置在掺杂阱内部的可选的浅沟槽隔离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式