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1. 发明申请

US20090032875A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090032875A1
公开(公告)日：2009-02-05
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke KAWAGUCHI , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与所述半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

2. 发明授权

US08008715B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08008715B2
公开(公告)日：2011-08-30
申请号：US12185630
申请日：2008-08-04
申请人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
发明人： Yusuke Kawaguchi , Kazuya Nakayama , Tsuyoshi Ohta , Takeshi Uchihara , Takahiro Kawano , Yuji Kato
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/7811
摘要： There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the first conductivity type, and also extending under the element region and the gate wiring; a gate electrode provided inside the trench in the element region with a gate insulating film interposed in between; and a gate electrode lead portion provided inside the trench under the gate wiring with the gate insulating film interposed in between, and contacting the gate wiring and the gate electrode.
摘要翻译：提供一种半导体器件，包括：第一导电类型的第一半导体层; 设置在第一导电类型的第一半导体层上的第二导电类型的第二半导体层; 选择性地设置在第二导电类型的第二半导体层的前表面部分上的第一导电类型的半导体区域; 设置成与半导体区域的表面接触的第一主电极; 设置在第一导电类型的第一半导体层的一侧的第二主电极，与设置有第二导电类型的第二半导体层的表面相对的一侧; 围绕设置有半导体区域的元件区域设置在第二导电类型的第二半导体层上的栅极布线; 穿过第二导电类型的第二半导体层的沟槽到达第一导电类型的第一半导体层，并且还在元件区域和栅极布线之下延伸; 设置在所述元件区域的所述沟槽内部的栅电极，其间插入有栅极绝缘膜; 以及栅极引线部分，其设置在栅极布线下方的沟槽内部，栅极绝缘膜介于其间并与栅极布线和栅电极接触。

3. 发明申请

US20110186927A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：US20110186927A1
公开(公告)日：2011-08-04
申请号：US13014436
申请日：2011-01-26
申请人： Yusuke KAWAGUCHI , Takahiro Kawano
发明人： Yusuke KAWAGUCHI , Takahiro Kawano
IPC分类号： H01L29/78
CPC分类号： H01L29/78
摘要： According to one embodiment, a power semiconductor device includes a first insulating film and a second insulating film. The first insulating film has a first dielectric constant and is formed on a bottom surface and a side surface of a trench formed by a second semiconductor layer. The trench is in contact with a fourth semiconductor layer and extends from a surface of the fourth semiconductor layer through a third semiconductor layer to the second semiconductor layer. The second insulating film is formed on a side surface of the trench formed by the third semiconductor layer and a side surface of the trench formed by the fourth semiconductor layer, being connected to the first insulating film. The second insulating film has a second dielectric constant higher than the first dielectric constant. The gate electrode is buried in the trench via the first and second insulating films.
摘要翻译：根据一个实施例，功率半导体器件包括第一绝缘膜和第二绝缘膜。第一绝缘膜具有第一介电常数，并且形成在由第二半导体层形成的沟槽的底表面和侧表面上。沟槽与第四半导体层接触并且从第四半导体层的表面延伸穿过第三半导体层到第二半导体层。第二绝缘膜形成在由第三半导体层形成的沟槽的侧表面和由第四半导体层形成的沟槽的侧表面上，连接到第一绝缘膜。第二绝缘膜具有高于第一介电常数的第二介电常数。栅电极通过第一和第二绝缘膜埋在沟槽中。

4. 发明授权

US07910440B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910440B2
公开(公告)日：2011-03-22
申请号：US11968403
申请日：2008-01-02
申请人： Tsuyoshi Ohta , Takahiro Kawano
发明人： Tsuyoshi Ohta , Takahiro Kawano
IPC分类号： H01L21/336
CPC分类号： H01L29/66727 , H01L29/0661 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.
摘要翻译：半导体器件包括：形成在半导体衬底中的第一沟槽; 形成在所述第一沟槽的表面上的栅极氧化膜; 以及沟槽栅极电极，其形成为通过栅极氧化膜掩埋第一沟槽。半导体器件还包括：形成在半导体衬底中的宽度比第一沟槽的宽度宽的第二沟槽; 以及形成为埋入第二沟槽的端子嵌入式绝缘层。半导体器件还包括：第三沟槽，其形成在半导体衬底中，宽度大于第二沟槽的宽度; 以及形成为埋入第三沟槽的沟槽接触电极。

5. 发明授权

US08502305B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08502305B2
公开(公告)日：2013-08-06
申请号：US13421816
申请日：2012-03-15
申请人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tsuyoshi Ohta , Tatsuya Nishiwaki , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/66
CPC分类号： H01L29/7813 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0856 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/66734 , H01L29/861
摘要： According to an embodiment, a semiconductor device includes a semiconductor layer of a first conductive type, a base region of a second conductive type provided on the semiconductor layer and a first contact region of a second conductive type provided on the base region. The device includes a gate electrode provided in a trench piercing through the first contact region and the base region, and an interlayer insulating film provided on the gate electrode and containing a first conductive type impurity element. The device further includes a source region of a first conductive type provided between the interlayer insulating film and the first contact region, the source region being in contact with a side face of the interlayer insulating film and extending in the base region.
摘要翻译：根据实施例，半导体器件包括第一导电类型的半导体层，设置在半导体层上的第二导电类型的基极区域和设置在基极区域上的第二导电类型的第一接触区域。该器件包括设置在穿过第一接触区域和基极区域的沟槽中的栅电极，以及设置在栅极上并包含第一导电型杂质元素的层间绝缘膜。该器件还包括设置在层间绝缘膜和第一接触区域之间的第一导电类型的源极区域，源极区域与层间绝缘膜的侧面接触并且在基极区域中延伸。

6. 发明申请

US20080164517A1 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080164517A1
公开(公告)日：2008-07-10
申请号：US11968403
申请日：2008-01-02
申请人： Tsuyoshi OHTA , Takahiro Kawano
发明人： Tsuyoshi OHTA , Takahiro Kawano
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/66727 , H01L29/0661 , H01L29/66734 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device according to the present invention includes: a first trench that is formed in a semiconductor substrate; a gate oxide film that is formed on a surface of the first trench; and a trench gate electrode that is formed so as to bury the first trench via the gate oxide film. The semiconductor device also includes: a second trench that is formed in the semiconductor substrate with a width wider than the width of the first trench; and a terminal-embedded insulation layer that is formed so as to bury the second trench. The semiconductor device further includes: a third trench that is formed in the semiconductor substrate with a width wider than the width of the second trench; and a trench contact electrode that is formed so as to bury the third trench.
摘要翻译：根据本发明的半导体器件包括：形成在半导体衬底中的第一沟槽; 形成在所述第一沟槽的表面上的栅极氧化膜; 以及沟槽栅极电极，其形成为通过栅极氧化膜掩埋第一沟槽。半导体器件还包括：形成在半导体衬底中的宽度比第一沟槽的宽度宽的第二沟槽; 以及形成为埋入第二沟槽的端子嵌入式绝缘层。半导体器件还包括：第三沟槽，其形成在半导体衬底中，宽度大于第二沟槽的宽度; 以及形成为埋入第三沟槽的沟槽接触电极。

7. 发明申请

US20130248995A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130248995A1
公开(公告)日：2013-09-26
申请号：US13607533
申请日：2012-09-07
申请人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
发明人： Tatsuya NISHIWAKI , Tsuyoshi Ota , Norio Yasuhara , Masatoshi Arai , Takahiro Kawano
IPC分类号： H01L29/78 , H01L21/82 , H01L27/088
CPC分类号： H01L29/7827 , H01L21/82 , H01L27/088 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/41775 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type, a base layer of a second conductivity type placed above the first semiconductor layer, a second semiconductor layer of the first conductivity type placed above the base layer, multiple gate electrodes having upper end is positioned above the upper surface of the base layer, a lower end positioned below the bottom of the base layer, and contacting the first semiconductor layer, the second semiconductor layer, and the base layer through a gate insulating film, insulating component arranged above the gate electrode in which the upper surface is positioned below the upper surface of the second semiconductor layer, and a conductive layer covering the second semiconductor layer from the upper end to the bottom end.
摘要翻译：半导体器件包括第一导电类型的第一半导体层，位于第一半导体层上方的第二导电类型的基极层，位于基极层之上的第一导电类型的第二半导体层，具有上端的多个栅电极位于所述基底层的上表面的上方，位于所述基底层的底部下方的下端，并且通过栅极绝缘膜与所述第一半导体层，所述第二半导体层和所述基底层接触，栅电极，其上表面位于第二半导体层的上表面下方，以及导电层，其从上端到底端覆盖第二半导体层。

8. 发明申请

US20080112478A1 Wireless communication apparatus having equalizer 有权
标题翻译：具有均衡器的无线通信装置
公开(公告)号：US20080112478A1
公开(公告)日：2008-05-15
申请号：US11979797
申请日：2007-11-08
申请人： Takahiro Kawano
发明人： Takahiro Kawano
IPC分类号： H03H7/30
CPC分类号： H04L25/03159 , H04L2025/03414
摘要： Receiving a transmission line estimation sequence, a wireless communication apparatus generates a transmission line characteristic estimation value for each of a plurality of sub-carriers and smoothes the transmission line characteristic estimation value of a target sub-carrier to be processed and the transmission line characteristic estimation value of its adjacent sub-carrier. The apparatus includes a determination unit for determining whether or not the adjacent sub-carrier, is a null sub-carrier and a smoothing unit for smoothing the transmission line characteristic estimation value of the target sub-carrier by excluding the transmission line characteristic estimation value of the adjacent sub-carrier determined as a null carrier by the determination unit.
摘要翻译：接收传输线估计序列，无线通信装置为多个副载波中的每一个生成传输线特性估计值，并对待处理的目标副载波的传输线特性估计值进行平滑化，并且传输线特性估计其相邻副载波的值。该装置包括用于确定相邻副载波是否为空子载波的确定单元和用于通过排除目标副载波的传输线特性估计值来平滑化的传输线特性估计值的平滑单元，所述相邻子载波由所述确定单元确定为空载波。

9. 发明授权

US06919249B2 Semiconductor device and its manufacturing method comprising a trench gate 失效
标题翻译：半导体器件及其制造方法包括沟槽栅极
公开(公告)号：US06919249B2
公开(公告)日：2005-07-19
申请号：US10778072
申请日：2004-02-17
申请人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
发明人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
IPC分类号： H01L21/336 , H01L29/08 , H01L29/417 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/086 , H01L29/0847 , H01L29/41766 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.
摘要翻译：半导体器件包括第一导电类型（2）的半导体层，靠近半导体层形成的基极区域（3），选择性地放置在基极区域上的源极区域（4），沟槽（T），绝缘栅极层（7）和设置在每个沟槽的内壁上的栅电极（6）以及连接到源极区的源电极（9）。源极区域在与源极电极的接触（4a）中的杂质浓度高于与栅极绝缘层接触的杂质浓度，并且与源极电极的接触（4a）中的杂质浓度也高于在与基地区的联系。

10. 发明授权

US06717210B2 Trench gate type semiconductor device and fabricating method of the same 有权
标题翻译：沟槽型半导体器件及其制造方法
公开(公告)号：US06717210B2
公开(公告)日：2004-04-06
申请号：US10289339
申请日：2002-11-07
申请人： Akio Takano , Takahiro Kawano
发明人： Akio Takano , Takahiro Kawano
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/4933 , H01L29/7397 , H01L29/7802
摘要： A trench gate type semiconductor device includes a first semiconductor layer having first and second main surfaces, a second semiconductor layer of a first conductivity type as formed on the first main surface of the first semiconductor layer, a third semiconductor layer of a second conductivity type as formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type as formed at a surface of the third semiconductor layer, a gate electrode having a polycrystalline silicon layer being buried in a trench formed to a depth reaching the second semiconductor layer from a surface of the fourth semiconductor layer with a gate insulating film interposed therebetween and having an upper end portion protruding upwardly from a trench upper end opening while having its width greater than a width of the trench and a metal silicide film formed at an upper surface and side surfaces of the upper end portion of the polycrystalline silicon layer, a first main electrode in contact with both the fourth third semiconductor layer, and a second main electrode formed at the second main surface of the first semiconductor layer.
摘要翻译：沟槽栅型半导体器件包括具有第一和第二主表面的第一半导体层，形成在第一半导体层的第一主表面上的第一导电类型的第二半导体层，第二导电类型的第三半导体层，形成在所述第二半导体层上的形成在所述第三半导体层的表面上的第一导电类型的第四半导体层，具有多晶硅层的栅电极被掩埋在形成为深度到达所述第二半导体层的深度的沟槽中所述第四半导体层的表面具有介于其间的栅极绝缘膜，并且具有从沟槽上端开口向上突出的上端部，同时其宽度大于所述沟槽的宽度，以及形成在上表面处的金属硅化物膜，多晶硅层的上端部的侧表面，第一主电极 de与第四第三半导体层接触，第二主电极形成在第一半导体层的第二主表面处。

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