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1. 发明授权

US07576392B2 Semiconductor device including gate wiring, main electrodes and connecting plate connected onto said main electrodes 有权
标题翻译：包括连接到所述主电极上的栅极布线，主电极和连接板的半导体器件
公开(公告)号：US07576392B2
公开(公告)日：2009-08-18
申请号：US10612925
申请日：2003-07-07
申请人： Takahiro Kawano , Kenichi Ogata , Tatsuo Yoneda
发明人： Takahiro Kawano , Kenichi Ogata , Tatsuo Yoneda
IPC分类号： H01L29/76
CPC分类号： H01L24/06 , H01L23/4824 , H01L23/49524 , H01L23/49562 , H01L24/05 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/37147 , H01L2224/40091 , H01L2224/40245 , H01L2224/4103 , H01L2224/48247 , H01L2224/48465 , H01L2224/49111 , H01L2224/73219 , H01L2224/73221 , H01L2224/84205 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01047 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor device disclosed herein comprises a semiconductor layer which includes a first semiconductor region of a first conductivity type, a base region of a second conductivity type, and a plurality of second semiconductor regions of the first conductivity type; a gate wiring which is formed on the semiconductor layer via a first insulating film; a plurality of main electrodes which are electrically connected to the plurality of second semiconductor regions and which are insulated from the gate wiring, wherein the gate wiring is arranged between the main electrodes and upper surfaces of the main electrodes are higher than an upper surface of the uppermost layer of the gate wiring; and a connecting plate which is directly connected onto uppermost layers of the main electrodes.
摘要翻译：本文公开的半导体器件包括半导体层，其包括第一导电类型的第一半导体区域，第二导电类型的基极区域和第一导电类型的多个第二半导体区域; 通过第一绝缘膜形成在半导体层上的栅极布线; 电连接到多个第二半导体区域并与栅极布线绝缘的多个主电极，其中布置在主电极和主电极的上表面之间的栅极布线高于栅极布线的最上层; 以及直接连接到主电极的最上层的连接板。

2. 发明授权

US06507088B2 Power semiconductor device including voltage drive type power MOS transistor 失效
标题翻译：功率半导体器件，包括电压驱动型功率MOS晶体管
公开(公告)号：US06507088B2
公开(公告)日：2003-01-14
申请号：US09811452
申请日：2001-03-20
申请人： Tatsuo Yoneda
发明人： Tatsuo Yoneda
IPC分类号： H01L2900
CPC分类号： H01L29/7813 , H01L27/0251 , H01L27/0629 , H01L29/7803 , H03K17/0822
摘要： A power semiconductor device of the present invention comprises a voltage drive type power MOS transistor, a series connection of a first resistor and Zener diode, a second resistor, and a series connection of a third resistor and MOS transistor. The power MOS transistor has a gate, source and drain. A drain-to-source voltage of the power MOS transistor is applied across the series connection of the first resistor and Zener diode. A gate-to-source voltage of the power MOS transistor is applied across the second resistor. The gate-to-source voltage of the power MOS transistor is applied across a series connection of a third resistor and the MOS transistor. The MOS transistor has a gate, source and drain. The gate of the MOS transistor is connected to a node between the first resistor and the Zener diode.
摘要翻译：本发明的功率半导体器件包括电压驱动型功率MOS晶体管，第一电阻器和齐纳二极管的串联连接，第二电阻器和第三电阻器和MOS晶体管的串联连接。功率MOS晶体管具有栅极，源极和漏极。功率MOS晶体管的漏极 - 源极电压施加在第一电阻器和齐纳二极管的串联连接之间。功率MOS晶体管的栅极 - 源极电压跨越第二电阻器施加。功率MOS晶体管的栅极 - 源极电压跨越第三电阻器和MOS晶体管的串联连接。 MOS晶体管具有栅极，源极和漏极。 MOS晶体管的栅极连接到第一电阻和齐纳二极管之间的节点。

3. 发明授权

US06750511B2 Trench-gate semiconductor device 失效
标题翻译：沟槽栅半导体器件
公开(公告)号：US06750511B2
公开(公告)日：2004-06-15
申请号：US10246468
申请日：2002-09-19
申请人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
发明人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
IPC分类号： H01L2976
CPC分类号： H01L29/086 , H01L29/0847 , H01L29/41766 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.
摘要翻译：半导体器件包括第一导电类型（2）的半导体层，靠近半导体层形成的基极区域（3），选择性地放置在基极区域上的源极区域（4），沟槽（T），绝缘栅极层（7）和设置在每个沟槽的内壁上的栅电极（6）以及连接到源极区的源电极（9）。源极区域与源电极的接触（4a）中的杂质浓度高于与栅极绝缘层接触的杂质浓度，并且与源电极的接触（4a）中的杂质浓度也高于接触与基地区。

4. 发明授权

US06919249B2 Semiconductor device and its manufacturing method comprising a trench gate 失效
标题翻译：半导体器件及其制造方法包括沟槽栅极
公开(公告)号：US06919249B2
公开(公告)日：2005-07-19
申请号：US10778072
申请日：2004-02-17
申请人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
发明人： Takahiro Kawano , Tatsuo Yoneda , Hirobumi Matsuki
IPC分类号： H01L21/336 , H01L29/08 , H01L29/417 , H01L29/78 , H01L21/8238
CPC分类号： H01L29/086 , H01L29/0847 , H01L29/41766 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device comprises a semiconductor layer of a first conductivity type (2), a base region (3) formed proximal to the semiconductor layer, a source region (4) selectively placed over the base region, trenches (T), a gate insulating layer (7) and a gate electrode (6) provided on an inner wall of each of the trenches, and a source electrode (9) connected to the source region. The source region is higher in impurity concentration in a contact (4a) with the source electrode than in a contact with the gate insulating layer, and it is also higher in impurity concentration in the contact (4a) with the source electrode than in a contact with the base region.
摘要翻译：半导体器件包括第一导电类型（2）的半导体层，靠近半导体层形成的基极区域（3），选择性地放置在基极区域上的源极区域（4），沟槽（T），绝缘栅极层（7）和设置在每个沟槽的内壁上的栅电极（6）以及连接到源极区的源电极（9）。源极区域在与源极电极的接触（4a）中的杂质浓度高于与栅极绝缘层接触的杂质浓度，并且与源极电极的接触（4a）中的杂质浓度也高于在与基地区的联系。

5. 发明授权

US06690061B2 MOS Semiconductor device 有权
标题翻译： MOS半导体器件
公开(公告)号：US06690061B2
公开(公告)日：2004-02-10
申请号：US10253522
申请日：2002-09-25
申请人： Tatsuo Yoneda , Bungo Tanaka
发明人： Tatsuo Yoneda , Bungo Tanaka
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L27/088 , H01L29/456 , H01L2224/13 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012
摘要： The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.
摘要翻译：根据本发明的一个方面的半导体器件包括：第一导电类型的半导体衬底; 形成在半导体衬底的主表面上的第一导电类型的第一半导体层，第一半导体层的杂质浓度低于半导体衬底的杂质浓度; 形成在所述第一半导体层上的第二导电类型的第二和第三半导体层，所述第二和第三半导体层彼此隔离; 形成在第二和第三半导体层中的第一导电类型的第一和第二MOS晶体管MOS1和MOS2，作为第一和第二MOS晶体管的漏极的第一半导体层和半导体衬底; 和导电层。

6. 发明授权

US06521954B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06521954B1
公开(公告)日：2003-02-18
申请号：US10023942
申请日：2001-12-21
申请人： Shigeo Kouzuki , Yasunori Usui , Tatsuo Yoneda
发明人： Shigeo Kouzuki , Yasunori Usui , Tatsuo Yoneda
IPC分类号： H01L2972
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/66712
摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type juxtaposed on a semiconductor substrate of the first conductivity type. The first semiconductor layer has an impurity concentration lower than that of the semiconductor substrate. The second semiconductor layer has at a central location a trench, which extends from the upper end toward the semiconductor substrate. A first region of the second conductivity type is formed to include an upper portion of the second semiconductor layer. A second region of the first conductivity type is formed in a surface of the first region. A gate electrode is disposed, through an insulating film, on a channel region, which is a surface portion of the first region between the second region and an upper portion of the first semiconductor layer.
摘要翻译：半导体器件包括并排在第一导电类型的半导体衬底上的第一导电类型的第一半导体层和第二导电类型的第二半导体层。第一半导体层的杂质浓度低于半导体衬底的杂质浓度。第二半导体层在中心位置具有从上端向半导体衬底延伸的沟槽。形成第二导电类型的第一区域以包括第二半导体层的上部。第一导电类型的第二区域形成在第一区域的表面中。栅电极通过绝缘膜设置在作为第一区域的第一区域和第一半导体层的上部之间的第一区域的表面部分的沟道区上。

7. 发明授权

US5420450A Semiconductor device having stable breakdown voltage in wiring area 失效
标题翻译：半导体器件在布线区域具有稳定的击穿电压
公开(公告)号：US5420450A
公开(公告)日：1995-05-30
申请号：US320643
申请日：1994-10-11
申请人： Tatsuo Yoneda , Kazuaki Suzuki
发明人： Tatsuo Yoneda , Kazuaki Suzuki
IPC分类号： H01L29/10 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/42316
摘要： A semiconductor device having stable breakdown voltage in wiring area. The semiconductor has a first conducting type semiconductor substrate with a plurality of second conducting type first semiconductor regions formed on one part of the surface of the first conducting type semiconductor substrate. A first conducting type high density diffused second semiconductor region is formed on one part of the surface within the second conducting type first semiconductor region. A gate electrode material extends across one part of the surface of the first conducting type semiconductor substrate, where one part of the surface of the first conducting type high density diffused second semiconductor region and the second conducting type first semiconductor region are not formed. An insulating film covers the gate electrode material and a metal source wiring is connected to the first conducting type high density diffused second semiconductor region and the second conducting type first semiconductor region. A metal gate wiring is connected to one part of the surface of the gate electrode material through an open section provided in the insulating film, and second conducting type third semiconductor regions are formed as a plurality of partitions on the surface of the first conducting type semiconductor substrate on the lower part of the metal gate wiring. In the semiconductor device, the second conducting type third semiconductor region is positioned to approach the limit reached by a depletion layer extending from the second conducting type third semiconductor region toward the first conducting type semiconductor substrate.
摘要翻译：一种在布线区域具有稳定的击穿电压的半导体器件。半导体具有形成在第一导电型半导体衬底的表面的一部分上的多个第二导电型第一半导体区域的第一导电型半导体衬底。第一导电型高密度扩散第二半导体区域形成在第二导电型第一半导体区域内的表面的一部分上。栅电极材料延伸穿过第一导电型半导体衬底的表面的一部分，其中第一导电型高密度扩散第二半导体区域和第二导电型第一半导体区域的表面的一部分未形成。绝缘膜覆盖栅电极材料，并且金属源布线连接到第一导电型高密度扩散第二半导体区域和第二导电型第一半导体区域。金属栅极布线通过设置在绝缘膜上的开口部与栅极材料的一部分连接，第二导电型第三半导体区域形成为第一导电型半导体的表面上的多个隔板基板在金属栅极布线的下部。在半导体器件中，第二导电型第三半导体区域被定位成接近由从第二导电类型第三半导体区域向第一导电型半导体衬底延伸的耗尽层达到的极限。

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