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1. 发明申请

US20130248998A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130248998A1
公开(公告)日：2013-09-26
申请号：US13619336
申请日：2012-09-14
申请人： Shinichiro Misu , Tsuyoshi Ota , Tatsuya Nishiwaki , Takeshi Uchihara , Yusuke Kawaguchi
发明人： Shinichiro Misu , Tsuyoshi Ota , Tatsuya Nishiwaki , Takeshi Uchihara , Yusuke Kawaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7801 , H01L29/0623 , H01L29/0634 , H01L29/0878 , H01L29/407 , H01L29/4175 , H01L29/42368 , H01L29/42376 , H01L29/66704 , H01L29/66734 , H01L29/66787 , H01L29/7813 , H01L29/7825 , H01L29/872
摘要： According to one embodiment, a semiconductor device includes, a drain, source, base and drift regions, a gate electrode, a gate insulating film, a first semiconductor region, a drain electrode, and a source electrode. The drain region has a first portion, and a second portion having a surface extending in a first direction which is vertical to a main surface of the first portion. The source region extends in a second direction which is parallel to the second portion, and is provided to be spaced from the drain region. The gate electrode extends in the first direction and a third direction which is vertical to the first direction and the second direction, and passes through the base region in the third direction. The first semiconductor region is provided between the gate insulating film and the drain region, and has a lower impurity concentration than the drift region.
摘要翻译：根据一个实施例，半导体器件包括漏极，源极，基极和漂移区，栅电极，栅绝缘膜，第一半导体区，漏电极和源电极。漏区具有第一部分，第二部分具有沿垂直于第一部分的主表面的第一方向延伸的表面。源极区域在与第二部分平行的第二方向上延伸，并且设置成与漏极区域间隔开。栅极电极在第一方向和与第一方向和第二方向垂直的第三方向上延伸，并且在第三方向上穿过基极区域。第一半导体区域设置在栅极绝缘膜和漏极区之间，并且具有比漂移区更低的杂质浓度。

2. 发明申请

US20120086073A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：功率半导体器件及其制造方法
公开(公告)号：US20120086073A1
公开(公告)日：2012-04-12
申请号：US13327644
申请日：2011-12-15
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/66734 , H01L29/7813
摘要： A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.
摘要翻译：垂直功率半导体器件包括形成在电池部分和终端部分中的第一导电类型的第一半导体层，围绕电池部分的端接部分，形成在第一半导体层上的第二导电类型的第二半导体层单元部分，部分地形成在第二半导体层上的第一导电类型的第三半导体层和形成在终端部分中的第一半导体层上的第二导电类型的保护环层。保护环层中的净杂质浓度一般是倾斜的，在其下侧相对较高，而在其上侧相对较低。或者，保护环层中的净杂质浓度恒定。

3. 发明申请

US20120068248A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20120068248A1
公开(公告)日：2012-03-22
申请号：US13233993
申请日：2011-09-15
申请人： Yusuke KAWAGUCHI
发明人： Yusuke KAWAGUCHI
IPC分类号： H01L29/788 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0626 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/7805 , H01L29/7808
摘要： According to one embodiment, a semiconductor device, includes an element unit including a vertical-type MOSFET, the vertical-type MOSFET in including a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer sequentially stacked in order, an impurity concentration of the second semiconductor layer being lower than the first semiconductor layer, an insulator covering inner surfaces of a plurality of trenches, the adjacent trenches being provided with a first interval in between, and a diode unit including basically with the units of the element unit, the adjacent trenches being provided with a second interval in between, the second interval being larger than the first interval.
摘要翻译：根据一个实施例，半导体器件包括包括垂直型MOSFET的元件单元，包括第一半导体层的垂直型MOSFET，第二半导体层，第三半导体层，第四半导体层，第五半导体层层，所述第二半导体层的杂质浓度低于所述第一半导体层，绝缘体覆盖多个沟槽的内表面，所述相邻沟槽之间设置有第一间隔，二极管单元包括：基本上与元件单元的单元相邻，相邻沟槽之间设置有第二间隔，第二间隔大于第一间隔。

4. 发明授权

US07919811B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07919811B2
公开(公告)日：2011-04-05
申请号：US12122165
申请日：2008-05-16
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a second-conductivity-type base region provided on a first-conductivity-type semiconductor layer, a first-conductivity-type source region provided on the second-conductivity-type base region, a gate insulating film covering an inner wall of a trench which passes through the second-conductivity-type base region and reaching the first-conductivity-type semiconductor layer, a gate electrode buried in the trench via the gate insulating film, and a second-conductivity-type region being adjacent to the second-conductivity-type base region below the first-conductivity-type source region, spaced from the gate insulating film, and having a higher impurity concentration than the second-conductivity-type base region. c≧d is satisfied, where d is a depth from an upper surface of the first-conductivity-type source region to a lower end of the gate electrode, and c is a depth from an upper surface of the first-conductivity-type source region to a lower surface of the second-conductivity-type base region.
摘要翻译：半导体器件包括设置在第一导电型半导体层上的第二导电型基极区域，设置在第二导电型基极区域上的第一导电型源极区域，覆盖内壁的栅极绝缘膜通过所述第二导电型基极区域并到达所述第一导电型半导体层的沟槽，经由所述栅极绝缘膜埋设在所述沟槽中的栅电极，以及与所述第二导电型基极区相邻的第二导电型区域与第一导电型源极区域相邻的第二导电型基极区域，与栅极绝缘膜间隔开，并且具有比第二导电型基极区域更高的杂质浓度。 c≥d，其中d是从第一导电型源极区的上表面到栅电极的下端的深度，c是从第一导电型源的上表面的深度区域延伸到第二导电型基极区域的下表面。

5. 发明申请

US20090242977A1 SEMICONDUCTOR DEVICE AND DC-DC CONVERTER 有权
标题翻译：半导体器件和DC-DC转换器
公开(公告)号：US20090242977A1
公开(公告)日：2009-10-01
申请号：US12408056
申请日：2009-03-20
申请人： Yusuke KAWAGUCHI , Miwako Akiyama , Yoshihiro Yamaguchi , Nobuyuki Sato , Shigeaki Hayase
发明人： Yusuke KAWAGUCHI , Miwako Akiyama , Yoshihiro Yamaguchi , Nobuyuki Sato , Shigeaki Hayase
IPC分类号： H01L29/78
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/42368 , H01L29/66666 , H01L29/7803 , H01L29/7813 , H01L29/7827 , H02M3/1588 , Y02B70/1466
摘要： A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor region provided in the semiconductor substrate; a first trench formed in the semiconductor region; a second trench formed in the semiconductor substrate; a trench gate electrode provided in the first trench; and a trench source electrode provided in the second trench. The trench source electrode is shaped like a stripe and connected to the source electrode through its longitudinal portion.
摘要翻译：半导体器件包括：第一导电类型的半导体衬底; 设置在所述半导体衬底中的半导体区域; 形成在半导体区域中的第一沟槽; 形成在所述半导体衬底中的第二沟槽; 设置在所述第一沟槽中的沟槽栅电极; 以及设置在第二沟槽中的沟槽源电极。沟槽源电极的形状像条纹，并通过其纵向部分连接到源电极。

6. 发明授权

US07566933B2 Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device 有权
标题翻译：沟槽栅半导体器件及沟槽栅极半导体器件的制造方法
公开(公告)号：US07566933B2
公开(公告)日：2009-07-28
申请号：US11484664
申请日：2006-07-12
申请人： Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono
发明人： Yoshihiro Yamaguchi , Yusuke Kawaguchi , Syotaro Ono
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/66734
摘要： Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.
摘要翻译：公开了一种沟槽栅半导体器件，包括：沟槽栅极结构; 具有第一导电类型的源极层，经由栅极绝缘膜面对栅电极，并具有顶面; 具有第二导电类型的基底层，与源极层相邻，并且经由栅极绝缘膜面对栅电极; 具有第一导电类型的半导体层，与基底层相邻，并且经由栅极绝缘膜面对栅电极而不接触源极层; 以及具有第二导电类型的接触层，与源极层和基极层接触，具有与源极层的顶部平面连续的顶面，并且具有两个或更多个沿着深度方向的杂质浓度值分布中的峰峰位于比源层的形成深度浅的位置。

7. 发明申请

US20090146209A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090146209A1
公开(公告)日：2009-06-11
申请号：US12332260
申请日：2008-12-10
申请人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Miwako Akiyama , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0634 , H01L29/0869 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a main surface of the first semiconductor layer and having a lower impurity concentration than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type selectively provided on the third semiconductor layer; a gate electrode provided in a trench passing through the third semiconductor layer and reaching the second semiconductor layer; a first main electrode contacting the fourth semiconductor layer and contacting the third semiconductor layer through a contact groove provided to pass through the fourth semiconductor layer between the contiguous gate electrodes; a second main electrode provided on an opposite surface to the main surface of the first semiconductor layer; and a fifth semiconductor layer of the second conductivity type provided in an interior portion of the second semiconductor layer corresponding to a part under the contact groove. An uppermost portion of the fifth semiconductor layer contacts the third semiconductor layer, a lowermost portion of the fifth semiconductor layer has a higher impurity concentration than that of the other portion in the fifth semiconductor layer and is located in the second semiconductor layer and not contacting the first semiconductor layer, and the fifth semiconductor layer is narrower from the uppermost portion to the lower most portion.
摘要翻译：半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层设置在第一半导体层的主表面上并且具有比第一半导体层的杂质浓度低的第二半导体层; 设置在第二半导体层上的第二导电类型的第三半导体层; 选择性地设置在第三半导体层上的第一导电类型的第四半导体层; 设置在穿过所述第三半导体层并到达所述第二半导体层的沟槽中的栅电极; 与所述第四半导体层接触的第一主电极，并且通过设置成在所述连续的栅电极之间穿过所述第四半导体层的接触槽使所述第三半导体层接触; 设置在与所述第一半导体层的主表面相反的表面上的第二主电极; 以及第二导电类型的第五半导体层，设置在与所述接触槽下方的部分对应的所述第二半导体层的内部。第五半导体层的最上部与第三半导体层接触，第五半导体层的最下部分的杂质浓度比第五半导体层中的其他部分杂质浓度高，位于第二半导体层中，第一半导体层，第五半导体层从最上部到最下部较窄。

8. 发明授权

US07541643B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07541643B2
公开(公告)日：2009-06-02
申请号：US11399448
申请日：2006-04-07
申请人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
发明人： Syotaro Ono , Wataru Saito , Yusuke Kawaguchi
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/402 , H01L29/41741 , H01L29/7811
摘要： This semiconductor device comprises a pillar layer including a first semiconductor pillar layer of a first conductivity type and a second semiconductor pillar layer of a second conductivity type formed alternately on a first semiconductor layer. At the same depth position in the device region and the end region, a difference between an impurity concentration [cm-3] of the second semiconductor pillar layer in the device region and that of the second semiconductor pillar layer in the end region is less than plus or minus 5%. A width W11 [um] of the first semiconductor pillar layer in the device region, a width W21 [um] of the second semiconductor pillar layer in the device region, a width W12 [um] of the first semiconductor pillar layer in the end region, and a width W22 [um] of the second semiconductor pillar layer in the end region, meet the relationship of W21/W11
摘要翻译：该半导体器件包括：交替地在第一半导体层上形成的包括第一导电类型的第一半导体柱层和第二导电类型的第二半导体柱层的柱层。在器件区域和端部区域的相同深度位置处，器件区域中的第二半导体柱层的杂质浓度[cm-3]与末端区域中的第二半导体柱层的杂质浓度[cm-3]之间的差小于加或减5％。器件区域中的第一半导体柱层的宽度W11 [μm]，器件区域中的第二半导体柱层的宽度W21 [μm]，端部区域中的第一半导体柱层的宽度W12 [μm] ，并且端部区域中的第二半导体柱层的宽度W22 [μm]满足W21 / W11

9. 发明授权

US07489018B2 Transistor 失效
标题翻译：晶体管
公开(公告)号：US07489018B2
公开(公告)日：2009-02-10
申请号：US11405672
申请日：2006-04-18
申请人： Mitsuhiko Kitagawa , Takashi Nishimura , Yusuke Kawaguchi , Syotaro Ono
发明人： Mitsuhiko Kitagawa , Takashi Nishimura , Yusuke Kawaguchi , Syotaro Ono
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696 , H01L29/4933 , H01L29/7397 , H01L29/7824 , H01L29/7831 , H01L29/78603 , H01L29/78624
摘要： A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.
摘要翻译：晶体管包括：绝缘层; 设置在所述绝缘层的主表面上的半导体层; 设置在所述基底区域上的栅极绝缘层; 以及设置在栅极绝缘层上的栅电极。半导体层具有源极部分，具有多个第一导电类型的源极区域和多个第二导电类型的基极接触区域，源极区域与基极接触区域交替，第一导电类型的漏极部分以及设置在源极部分和漏极部分之间的第二导电类型的基极区域，基极区域与源极区域和基极接触区域接触。源极区域和基极区域之间的接合部比基极接触区域和基极区域之间的接合部更靠近漏极部分侧。

10. 发明申请

US20070194372A1 TRENCH-GATED MOSFET INCLUDING SCHOTTKY DIODE THEREIN 有权
标题翻译：包含肖特基二极管的TRENCH-GFET MOSFET
公开(公告)号：US20070194372A1
公开(公告)日：2007-08-23
申请号：US11740045
申请日：2007-04-25
申请人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
发明人： Syotaro Ono , Akio Nakagawa , Yusuke Kawaguchi , Yoshihiro Yamaguchi
IPC分类号： H01L31/00
CPC分类号： H01L29/7813 , H01L29/1095
摘要： Disclosed is a trench MOSFET, including: a trench gate structure having a gate electrode and a gate insulating film; an n-type diffusion layer formed to face the gate electrode via the gate insulating film at an upper portion of the trench; a p-type base layer formed to face the gate electrode via the gate insulating film at a lower portion than the upper portion; an n-type epitaxial layer locating to face the gate electrode via the gate insulating film at a further lower portion than the lower portion; a metal layer formed departing from the trench in parallel with a depth direction of the trench, penetrating the n-type diffusion layer and the p-type base layer, to reach the n-type epitaxial layer; and a p-type layer with higher impurity concentration than the p-type base layer, locating to be in contact with the p-type base layer and the metal layer.
摘要翻译：公开了一种沟槽MOSFET，其包括：具有栅极电极和栅极绝缘膜的沟槽栅极结构; 形成为在沟槽的上部经由栅极绝缘膜与栅电极对置的n型扩散层; p型基底层，其在比上部更低的一部分处经由栅极绝缘膜形成为面对栅电极; n型外延层，其定位成在比下部更下方的一部分经由栅极绝缘膜面对栅电极; 与沟槽的深度方向平行地形成的穿过n型扩散层和p型基底层的金属层，以到达n型外延层; 以及比p型基底层高的杂质浓度的p型层，与p型基底层和金属层接触。

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