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1. 发明授权

US06172915B2 Unified erase method in flash EEPROM 有权
标题翻译：闪存EEPROM中的统一擦除方法
公开(公告)号：US06172915B2
公开(公告)日：2001-01-09
申请号：US09408705
申请日：1999-09-30
申请人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
发明人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C8/12
摘要： A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.
摘要翻译：在用于执行单扇区，多扇区或全扇区擦除操作的闪存EEPROM存储器单元阵列中使用的统一擦除方法，其具有减少的总擦除时间量和均匀的VT分布与单扇区擦除操作一样好。如果其对应的擦除信号没有关闭，则从第一扇区到最后扇区的多个扇区中顺序执行擦除验证操作，从每个扇区的第一地址开始。每个扇区的当前地址存储在擦除验证操作失败的点。擦除脉冲仅对未通过擦除验证操作的所有扇区同时施加。然后从存储的当前地址开始重复擦除验证操作。当在多个扇区的所有扇区中已经关闭了擦除信号时，结束擦除操作。

2. 发明授权

US06222771B1 Unified program method and circuitry in flash EEPROM 有权
标题翻译：闪存EEPROM中的统一程序方法和电路
公开(公告)号：US06222771B1
公开(公告)日：2001-04-24
申请号：US09494456
申请日：2000-01-31
申请人： Yuan Tang , James C. Yu
发明人： Yuan Tang , James C. Yu
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5628 , G11C16/10 , G11C16/3468 , G11C2211/5624
摘要： A unified program method and circuitry for performing concurrently a programming and verifying operation in an array of Flash EEPROM memory cells is provided. Each of the memory cells includes a floating gate array core transistor. A single bandgap voltage is provided which corresponds to a predetermined amount of drain current at which programming is to be terminated. A program voltage is selectively connected to at least one of the columns of array bit lines containing the array core transistor which is to be programmed. A control gate bias voltage corresponding to a programmable memory state is selectively connected to the gate of the array core transistor. A core cell current flowing through the array core transistor and the predetermined amount of drain current is compared. The program voltage is disconnected so as to terminate automatically programming of the array core transistor when the core cell current falls below the predetermined amount of drain current.
摘要翻译：提供了一种统一的程序方法和电路，用于同时执行闪存EEPROM存储单元阵列中的编程和验证操作。每个存储单元包括浮栅阵列核心晶体管。提供单个带隙电压，其对应于将终止编程的预定量的漏极电流。选择性地将编程电压连接到包含待编程的阵列芯晶体管的阵列位线列中的至少一列。对应于可编程存储器状态的控制栅极偏置电压选择性地连接到阵列核心晶体管的栅极。比较流过阵列核心晶体管的核心单元电流和预定量的漏极电流。程序电压被断开，从而当核心单元电流低于预定的漏极电流量时自动编程阵列核心晶体管。

3. 发明授权

US6023426A Method of achieving narrow V.sub.T distribution after erase in flash EEPROM 失效
标题翻译：在闪存EEPROM中擦除后实现窄VT分布的方法
公开(公告)号：US6023426A
公开(公告)日：2000-02-08
申请号：US36971
申请日：1998-03-09
申请人： Yuan Tang , James C. Yu , Chien-Sheng Su
发明人： Yuan Tang , James C. Yu , Chien-Sheng Su
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/3404
摘要： There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.
摘要翻译：提供了一种在擦除之后校正闪存EEPROM存储单元中的过度存储单元的方法，以产生窄的阈值电压分布宽度。将地电势施加到存储器单元阵列中的所有单元的源和衬底。第一正脉冲电压以字线为单位，以字线的第一定时序列同时施加到每个字线。当第一正脉冲电压被施加到第一字线时，第二正时脉冲电压以位线为单位的第二定时序列同时施加到每个位线，然后对于每个后续字线重复，直到最后一个字线被应用。

4. 发明授权

US5805502A System for constant field erasure in a FLASH EPROM 失效
标题翻译： FLASH EPROM中常量字段擦除的系统
公开(公告)号：US5805502A
公开(公告)日：1998-09-08
申请号：US795024
申请日：1997-02-04
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

5. 发明授权

US5629893A System for constant field erasure in a flash EPROM 失效
标题翻译：闪存EPROM中的常量字段擦除系统
公开(公告)号：US5629893A
公开(公告)日：1997-05-13
申请号：US634512
申请日：1996-04-18
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

6. 发明授权

US06175598B1 Output noise control scheme for multiple I/O's 失效
标题翻译：输出噪声控制方案为多个I / O
公开(公告)号：US06175598B1
公开(公告)日：2001-01-16
申请号：US09032888
申请日：1998-03-02
申请人： James C. Yu , Chih-Liang Chen
发明人： James C. Yu , Chih-Liang Chen
IPC分类号： H03K190175
CPC分类号： H03K19/00361
摘要： An output noise control circuit with significantly reduced power/ground bounce characteristics when multiple outputs thereof are being simultaneously switched is provided. The output noise control circuit includes a plurality of output buffers each being formed of an output driver stage, a first pre-driver stage, and a second pre-driver stage. Each of the output driver stages includes a pull-up drive transistor and a pull-down drive transistor. Each of the first pre-driver stages includes a first inverter, and each of said second pre-driver stages includes a second inverter. A shared pull-up resistor has its one end coupled to each of the first pre-driver stage inverters and its other end connected to a ground potential node. A shared pull-down resistor has its one end coupled to each of the second pre-driver stage inverters and its other end connected to a power supply potential node. The output noise control circuit is formed with a reduced number of circuit components than the traditional output buffer circuits currently available.
摘要翻译：提供了当其多个输出被同时切换时具有显着降低的功率/接地反弹特性的输出噪声控制电路。输出噪声控制电路包括多个输出缓冲器，每个输出缓冲器由输出驱动器级，第一预驱动级和第二预驱动级形成。每个输出驱动级包括上拉驱动晶体管和下拉驱动晶体管。第一预驱动器级中的每一个包括第一反相器，并且每个所述第二预驱动级包括第二反相器。共享上拉电阻器的一端耦合到每个第一预驱动级反相器，其另一端连接到地电位节点。共享下拉电阻器的一端耦合到每个第二预驱动级反相器，而另一端连接到电源电位节点。输出噪声控制电路与目前可用的传统输出缓冲电路相比，电路组件数量减少。

7. 发明授权

US5559990A Memories with burst mode access 失效
标题翻译：具有突发模式访问的记忆
公开(公告)号：US5559990A
公开(公告)日：1996-09-24
申请号：US328337
申请日：1994-10-24
申请人： Pearl P. Cheng , Michael S. Briner , James C. Yu
发明人： Pearl P. Cheng , Michael S. Briner , James C. Yu
IPC分类号： G06F12/04 , G11C7/10 , G06F12/00
CPC分类号： G06F12/04 , G11C7/1018 , Y02B60/1225
摘要： To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.
摘要翻译：为了提供无边界突发模式访问，存储器阵列被分成两个或更多个子阵列。每个子阵列都有自己的行和列解码器。每个子阵列的列分为几组。为每组列提供读出放大器电路。每个子阵列的列解码器同时选择来自每个组的一列，使得所选列中的一行中的存储器位置具有连续的地址。所选行和列中的存储器位置由读出放大器电路读取。虽然一个子阵列的读出放大器电路的内容一个接一个地传送到存储器输出，另一个子阵列的连续的存储器位置被读取到读出放大器电路。在一些实施例中，为了节省功率，当它们的输出不被传送到存储器输出时，读出放大器电路被禁止。

8. 发明授权

US4476476A CMOS Input and output protection circuit 失效
标题翻译： CMOS输入和输出保护电路
公开(公告)号：US4476476A
公开(公告)日：1984-10-09
申请号：US249934
申请日：1981-04-01
申请人： James C. Yu , Suman H. Patel
发明人： James C. Yu , Suman H. Patel
IPC分类号： H01L27/02 , H01L27/092 , H01L27/04
CPC分类号： H01L27/0251 , H01L27/0921
摘要： A CMOS gate protection diode clamping the input terminal to substrate potential is prevented from injecting carriers into the substrate and causing SCR latchup by forming the diode as a well to substrate junction, surrounded by another, reverse-biased, well, to both reduce injection and collect parasitic injected carriers before they can diffuse to cause latchup.
摘要翻译：防止将输入端子钳位到衬底电位的CMOS栅极保护二极管将载流子注入到衬底中，并且通过将二极管形成为衬底结，并被另一个反向偏压阱包围，从而使SCR闭锁，以减少注入和收集寄生注射载体，然后才能扩散以引起闭锁。

9. 发明授权

US5790460A Method of erasing a flash EEPROM memory 失效
标题翻译：擦除闪存EEPROM存储器的方法
公开(公告)号：US5790460A
公开(公告)日：1998-08-04
申请号：US854619
申请日：1997-05-12
申请人： Chih-Liang Chen , I-Chuin Peter Chan , James C. Yu , Chien-Sheng Su , Chao-Ven Kao
发明人： Chih-Liang Chen , I-Chuin Peter Chan , James C. Yu , Chien-Sheng Su , Chao-Ven Kao
IPC分类号： G11C16/04 , G11C16/14 , G11C16/00
CPC分类号： G11C16/14
摘要： The invention is a novel erase method for erasing flash EEPROM memory devices. A memory cell of such a memory device has a first semiconductor region of one conductivity type formed in a second region of the opposite conductivity type, source and drain regions of the opposite conductivity type formed in the first semiconductor region, and a gate. The second region is formed within a substrate of the one conductivity type. The gate includes a control gate and a floating gate, which retains charge and overlies the first semiconductor region. The erase method of the invention includes the steps of: applying a first voltage of one polarity to the source region and the first and second semiconductor regions; and simultaneously applying a second voltage of the opposite polarity to the gate, whereby any charge on the floating gate tunnels through the floating gate dielectric into both the first region and the source region, thereby removing any charge retained by the floating gate.
摘要翻译：本发明是擦除闪存EEPROM存储器件的新颖的擦除方法。这种存储器件的存储单元具有形成在相反导电类型的第二区域中的一种导电类型的第一半导体区域，形成在第一半导体区域中的相反导电类型的源极和漏极区域以及栅极。第二区域形成在一种导电类型的衬底内。栅极包括控制栅极和浮置栅极，其保持电荷并覆盖第一半导体区域。本发明的擦除方法包括以下步骤：将一个极性的第一电压施加到源区和第一和第二半导体区; 并且同时向栅极施加相反极性的第二电压，由此浮置栅极上的任何电荷通过浮置栅极电介质隧穿到第一区域和源极区域中，从而去除由浮动栅极保留的任何电荷。

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