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1. 发明授权

US5559990A Memories with burst mode access 失效
标题翻译：具有突发模式访问的记忆
公开(公告)号：US5559990A
公开(公告)日：1996-09-24
申请号：US328337
申请日：1994-10-24
申请人： Pearl P. Cheng , Michael S. Briner , James C. Yu
发明人： Pearl P. Cheng , Michael S. Briner , James C. Yu
IPC分类号： G06F12/04 , G11C7/10 , G06F12/00
CPC分类号： G06F12/04 , G11C7/1018 , Y02B60/1225
摘要： To provide a boundaryless burst mode access, a memory array is divided into two or more subarrays. Each subarray has its own row and column decoders. The columns of each subarray are divided into groups. A sense amplifier circuit is provided for each group of columns. The column decoder of each subarray selects simultaneously one column from each group so that the memory locations in one row in the selected columns have consecutive addresses. The memory locations in the selected row and columns are read by the sense amplifier circuits. While the contents of the sense amplifier circuits of one subarray are transferred one by one to the memory output, consecutive memory locations of another subarray are read to the sense amplifier circuits. In some embodiments, to save power, sense amplifier circuits are disabled when their outputs are not transferred to the memory output.
摘要翻译：为了提供无边界突发模式访问，存储器阵列被分成两个或更多个子阵列。每个子阵列都有自己的行和列解码器。每个子阵列的列分为几组。为每组列提供读出放大器电路。每个子阵列的列解码器同时选择来自每个组的一列，使得所选列中的一行中的存储器位置具有连续的地址。所选行和列中的存储器位置由读出放大器电路读取。虽然一个子阵列的读出放大器电路的内容一个接一个地传送到存储器输出，另一个子阵列的连续的存储器位置被读取到读出放大器电路。在一些实施例中，为了节省功率，当它们的输出不被传送到存储器输出时，读出放大器电路被禁止。

2. 发明授权

US06914822B2 Read-biasing and amplifying system 失效
标题翻译：读偏置放大系统
公开(公告)号：US06914822B2
公开(公告)日：2005-07-05
申请号：US10786768
申请日：2004-02-25
申请人： Michael S. Briner
发明人： Michael S. Briner
IPC分类号： G11C7/02 , G11C7/06 , G11C11/34 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/06
CPC分类号： G11C16/24 , G11C7/062 , G11C16/26 , G11C16/28
摘要： A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.
摘要翻译：公开了一种用于闪速存储器的快速感测放大器，其包括多个浮动栅极存储器件，并且具有选择性地耦合到器件的列线。在读偏置和放大电路将特定存储器件的线路快速拉至读偏置电位之前，列线快速放电到地。该电位通过快速感测放大器内的差分放大器与感测参考电位进行比较。特定存储器件的二进制状态被提供为快速感测放大器的输出。

3. 发明授权

US06396739B2 Reference voltage generator using flash memory cells 有权
标题翻译：使用闪存单元的参考电压发生器
公开(公告)号：US06396739B2
公开(公告)日：2002-05-28
申请号：US09255763
申请日：1999-02-23
申请人： Michael S. Briner
发明人： Michael S. Briner
IPC分类号： G11C1134
CPC分类号： G05F3/242 , G11C5/147
摘要： First and second flash memory cells or transistors, operating in the linear region of operation, are provided with different threshold values by providing different charges on their respective floating gates. The first of the pair of flash memory transistors is “over-erased” until it has a negative threshold voltage so that the first flash memory transistor is rendered permanently conducting when its control gate and source are at Vss. Circuitry is provided for connecting the first and second flash memory transistors in parallel circuits in which equal current values are generated in an equilibrium condition. Circuitry for sensing a voltage in each of the parallel circuits is provided to determine any imbalance in current values and provide an output voltage which may be used as an reference value when the currents are in equilibrium. Circuitry is provided for sensing variations in the output voltage to vary the current through one of the flash memory transistors to bring the currents into equilibrium when the output voltage varies from the reference value provided at equilibrium. The control gate of the first (over-erased) flash memory transistor is connected to the system ground, Vss to further increase the stability of the reference voltage generator.
摘要翻译：在线性操作区域中操作的第一和第二闪存单元或晶体管通过在其各自的浮动栅极上提供不同的电荷而被提供有不同的阈值。一对闪存晶体管中的第一个被“过擦除”，直到其具有负阈值电压，使得当其控制栅极和源处于Vss时，第一闪存晶体管被永久导通。提供电路用于在并联电路中连接第一和第二闪存晶体管，其中在平衡条件下产生相等的电流值。提供用于感测每个并联电路中的电压的电路以确定电流值中的任何不平衡，并提供当电流处于平衡时可用作参考值的输出电压。提供电路用于检测输出电压的变化，以改变通过闪存晶体管之一的电流，以便当输出电压与平衡时提供的参考值变化时，使电流达到平衡。第一（过擦除）闪存晶体管的控制栅极连接到系统地Vss，以进一步提高参考电压发生器的稳定性。

4. 发明授权

US6094377A Memory circuit with switch for selectively connecting an input/output pad directly to a nonvolatile memory cell 有权
标题翻译：具有用于选择性地将输入/输出焊盘直接连接到非易失性存储单元的开关的存储器电路
公开(公告)号：US6094377A
公开(公告)日：2000-07-25
申请号：US251034
申请日：1999-02-18
申请人： Fariborz F. Roohparvar , Michael S. Briner
发明人： Fariborz F. Roohparvar , Michael S. Briner
IPC分类号： G11C16/26 , G11C29/48 , G11C7/00
CPC分类号： G11C16/26 , G11C29/48
摘要： An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like). In preferred embodiments, the test mode switch includes a set of series-connected pass transistors and a isolation voltage switch, the pass transistors pass test signals (indicative of test data to be written to or read from a selected cell) directly between the I/O pad and the selected cell in the test mode, and no signals pass through the pass transistors between the I/O pad and any memory cell in the normal mode. In the normal mode of such preferred embodiments, data to be written from the I/O pad to a selected cell passes through an input buffer before reaching the cell (or data to be read from a selected cell passes through an output buffer before reaching the I/O pad), and the isolation voltage switch holds a channel terminal of at least one of the pass transistors at a fixed supply voltage thereby preventing at least one of the pass transistors from undesirably switching on during the normal mode.
摘要翻译：一种在测试模式和正常操作模式下工作的集成电路，其包括改进的测试模式开关。在其中电路是集成存储器芯片的优选实施例的测试模式中，关闭测试模式开关，以便将输入/输出（I / O）焊盘直接连接到所选择的存储器单元（因此电流/电压表征的细胞）。在这些实施例的正常操作模式中，测试模式开关是断开的，并且即使在测试模式开关的晶体管不期望地导通的情况下（例如，由于 I / O焊盘上的低电压，电感耦合等）。在优选实施例中，测试模式开关包括一组串联连接的传输晶体管和隔离电压开关，传输晶体管直接将测试信号（指示要从所选单元写入或读取的测试数据）传送到I / O焊盘和测试模式下的所选单元，并且在正常模式下，没有信号通过I / O焊盘和任何存储单元之间的传输晶体管。在这样的优选实施例的正常模式中，要从I / O焊盘写入所选单元的数据在到达单元之前通过输入缓冲器（或将要从所选单元读取的数据在到达所述单元之前通过输出缓冲器 I / O焊盘），并且隔离电压开关将至少一个通过晶体管的沟道端子固定在固定的电源电压，从而防止至少一个通过晶体管在正常模式期间不期望地导通。

5. 发明授权

US6046615A Level detection circuit 失效
标题翻译：电平检测电路
公开(公告)号：US6046615A
公开(公告)日：2000-04-04
申请号：US094825
申请日：1998-06-15
申请人： Christophe J. Chevallier , Frankie F. Roohparvar , Michael S. Briner
发明人： Christophe J. Chevallier , Frankie F. Roohparvar , Michael S. Briner
IPC分类号： H03K17/22 , H03L7/00 , H03K5/22
CPC分类号： H03K17/223
摘要： A level detection circuit for monitoring the level of a power supply voltage and producing an output signal at power on for resetting various system elements powered by the supply voltage when the supply voltage reaches a predetermined level. The detection circuit, which is powered by the supply voltage includes a voltage reference circuit which produces a reference voltage having a magnitude which is relatively independent of the power supply voltage. A translator circuit functions to produce a translated voltage indicative of the supply voltage magnitudes and which is comparable in magnitude to the reference voltage when the supply voltage is at a suitable level such that the system will accept a power on reset pulse. A comparator circuit functions to compare the reference voltage with the translated voltage and cause an associated output circuit to issue the reset pulse. The reset circuit typically includes a one shot circuit, the output of which is logically ORed with the amplified comparator output. The amplified comparator output functions to hold the system elements in a reset state at very low supply voltages and the one shot output functions to reset the system elements once the supply voltage is at a sufficiently high level.
摘要翻译：电平检测电路，用于监视电源电压的电平并在通电时产生输出信号，以在电源电压达到预定电平时复位供电电压供电的各种系统元件。由电源电压供电的检测电路包括产生具有相对独立于电源电压的幅度的参考电压的电压参考电路。转换器电路用于产生指示电源电压幅度的转换电压，并且当电源电压处于适当电平时，其幅度与参考电压相当，使得系统将接受上电复位脉冲。比较器电路用于将参考电压与转换的电压进行比较，并使相关的输出电路发出复位脉冲。复位电路通常包括单稳态电路，其输出与放大的比较器输出逻辑或运算。放大的比较器输出用于在非常低的电源电压下将系统元件保持在复位状态，并且一次输出功能用于在电源电压处于足够高的水平时复位系统元件。

6. 发明授权

US5963061A Switch for minimizing transistor exposure to high voltage 有权
标题翻译：用于最大限度地减少晶体管暴露于高电压的开关
公开(公告)号：US5963061A
公开(公告)日：1999-10-05
申请号：US136681
申请日：1998-08-19
申请人： Michael S. Briner
发明人： Michael S. Briner
IPC分类号： H03K3/356 , H03K19/0185
CPC分类号： H03K3/356 , H03K19/0185
摘要： An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.
摘要翻译：将晶体管暴露于高电压最小化的非对称开关包括一对P沟道晶体管，其中两个N阱耦合回编程电压源和一对具有独立N阱的P沟道晶体管。还包括两对N沟道晶体管和反相电路，以向开关提供互补的输入电压。用作保护装置的P沟道和N沟道晶体管可能被相同的电压或单独的电压偏置。

7. 发明授权

US5862077A Fast sensing amplifier for flash memory 失效
标题翻译：闪存快速感应放大器
公开(公告)号：US5862077A
公开(公告)日：1999-01-19
申请号：US804951
申请日：1997-02-24
申请人： Michael S. Briner
发明人： Michael S. Briner
IPC分类号： G11C16/06 , G11C7/06 , G11C16/24 , G11C16/28 , G11C11/34
CPC分类号： G11C7/062 , G11C16/24 , G11C16/28
摘要： A fast-sensing amplifier for a flash memory comprised of a plurality of floating-gate memory devices and having a column line selectively coupled to the devices is disclosed. The column line is quickly discharged to ground before a read-biasing and amplifying circuit quickly pulls up the line to the read-bias potential at a particular memory device. This potential is compared to a sense-reference potential by a differential amplifier within the fast-sensing amplifier. The binary state of the particular memory device is provided as the output of the fast-sensing amplifier.
摘要翻译：公开了一种用于闪速存储器的快速感测放大器，其包括多个浮动栅极存储器件，并且具有选择性地耦合到器件的列线。在读偏置和放大电路将特定存储器件的线路快速拉至读偏置电位之前，列线快速放电到地。该电位通过快速感测放大器内的差分放大器与感测参考电位进行比较。特定存储器件的二进制状态被提供为快速感测放大器的输出。

8. 发明授权

US5677879A Method and apparatus for performing memory cell verification on a nonvolatile memory circuit 失效
标题翻译：用于在非易失性存储器电路上执行存储器单元验证的方法和装置
公开(公告)号：US5677879A
公开(公告)日：1997-10-14
申请号：US725008
申请日：1996-10-01
申请人： Fariborz F. Roohparvar , Michael S. Briner
发明人： Fariborz F. Roohparvar , Michael S. Briner
IPC分类号： G11C16/02 , G11C16/06 , G11C16/34 , G11C29/12 , G11C29/38 , G11C29/50 , G11C29/52 , G11C29/00
CPC分类号： G11C16/3445 , G11C16/3436 , G11C16/3459 , G11C29/38 , G11C29/52
摘要： A method for verifying the status of selected nonvolatile memory cells of an integrated memory circuit, such as during a memory erase or programming operation, and an integrated nonvolatile memory circuit including circuitry for performing this verification method. Preferably, the invention employs simple logic circuitry including a flip-flop to assert successful verification data only in response to a continuous validity of a verification signal throughout a sampling period, thereby avoiding false assertion of successful verification data. The sampling period is preferably longer than the expected duration of fluctuations due to noise in the verification signal. During the sampling period of a verification operation, the logic circuitry receives a raw verification signal indicative of the instantaneous relation between a measured threshold voltage of a selected memory cell and a reference voltage. The raw verification signal is valid if the threshold voltage has a desired relation to the reference voltage at an instant of time. The flip-flop remains in a first state while the raw verification signal is valid, but enters a second state in response to the raw verification signal going invalid and remains in the second state for the rest of the sampling period. An output signal from the logic circuitry indicates the state of the flip-flop at the end of the sampling period. A level of the output signal indicating that the flip-flop is in the first state at the end of the sampling period is interpreted as successful verification data.
摘要翻译：一种用于验证集成存储器电路的所选择的非易失性存储器单元的状态的方法，例如在存储器擦除或编程操作期间，以及包括用于执行该验证方法的电路的集成非易失性存储器电路。优选地，本发明采用简单的逻辑电路，包括触发器仅在响应于在整个采样周期内的验证信号的连续有效性来确认成功验证数据，从而避免成功验证数据的错误断言。采样周期优选地长于由于验证信号中的噪声引起的预期的波动持续时间。在验证操作的采样周期期间，逻辑电路接收指示所选存储单元的测量阈值电压与参考电压之间的瞬时关系的原始验证信号。如果阈值电压在时刻与参考电压具有期望的关系，则原始验证信号是有效的。当原始验证信号有效时，触发器保持在第一状态，但是响应于原始验证信号无效并进入第二状态，并且在采样周期的其余部分中保持第二状态。来自逻辑电路的输出信号指示在采样周期结束时触发器的状态。指示触发器在采样周期结束时处于第一状态的输出信号的电平被解释为成功的验证数据。

9. 发明授权

US5903504A Op amp circuit with variable resistance and memory system including same 失效
标题翻译：具有可变电阻的运算放大器电路和包括其的存储器系统
公开(公告)号：US5903504A
公开(公告)日：1999-05-11
申请号：US978734
申请日：1997-11-26
申请人： Christophe J. Chevallier , Michael S. Briner
发明人： Christophe J. Chevallier , Michael S. Briner
IPC分类号： G11C5/14 , G11C16/28 , G11C16/30 , H03G1/00 , H03G3/00 , G11C7/02
CPC分类号： H03G3/001 , G11C16/28 , G11C16/30 , G11C5/143 , H03G1/0088
摘要： An operational amplifier-based voltage multiplier circuit ("op amp circuit") implemented as an integrated circuit, and a memory chip including such an op amp circuit. The op amp circuit includes a variable operational feedback or input resistance (or a variable operational feedback resistance and a variable input resistance), and preferably also circuitry for controlling at least one variable resistance in response to control bits to cause the op amp circuit to assert a selected output voltage in response to a given input voltage. Preferably, each set of control bits determines a binary control word whose binary value has a simple functional relation to the value of the output voltage selected thereby. Preferably, the memory chip includes an array of memory cells (e.g, flash memory cells) and a control unit for controlling memory operations including programming, reading, and erasing the memory cells. The op amp circuit outputs each selected output voltage in response to a different binary control word asserted by the control unit. Each binary control word is preferably determined by a set of control bits whose binary value has a simple functional relation to the value of the output voltage selected thereby. The memory chip preferably includes non-volatile data storage units which store bits of the binary control words.
摘要翻译：实现为集成电路的基于运算放大器的电压倍增器电路（“运放电路”）以及包括这种运算放大器电路的存储器芯片。运算放大器电路包括可变运行反馈或输入电阻（或可变运行反馈电阻和可变输入电阻），并且优选地还包括用于响应于控制位来控制至少一个可变电阻以使运算放大器电路断言的电路响应给定输入电压的选择的输出电压。优选地，每组控制位确定二进制控制字，其二进制值与由此选择的输出电压的值具有简单的功能关系。优选地，存储器芯片包括存储器单元阵列（例如闪存单元）和用于控制存储器操作的控制单元，包括编程，读取和擦除存储器单元。运算放大器电路响应于由控制单元确定的不同的二进制控制字输出每个选择的输出电压。每个二进制控制字优选由一组控制位确定，其二进制值与由此选择的输出电压的值具有简单的功能关系。存储器芯片优选地包括存储二进制控制字的位的非易失性数据存储单元。

10. 发明授权

US5867042A Switch for minimizing transistor exposure to high voltage 失效
公开(公告)号：US5867042A
公开(公告)日：1999-02-02
申请号：US835763
申请日：1997-04-08
申请人： Michael S. Briner
发明人： Michael S. Briner
IPC分类号： H03K3/356 , H03K17/10 , H03K19/0185
CPC分类号： H03K3/356156 , H03K17/102 , H03K3/35606
摘要： An asymmetric switch which minimizes transistor exposure to high voltage includes one pair of P-channel transistors with both N-wells coupled back to the programming voltage source and one pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit are also included to provide complementary input voltages to the switch. The P-channel and N-channel transistors used as guard devices may be biased by the same voltage or separate voltages.

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