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1. 发明授权

US5629893A System for constant field erasure in a flash EPROM 失效
标题翻译：闪存EPROM中的常量字段擦除系统
公开(公告)号：US5629893A
公开(公告)日：1997-05-13
申请号：US634512
申请日：1996-04-18
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

2. 发明授权

US5805502A System for constant field erasure in a FLASH EPROM 失效
标题翻译： FLASH EPROM中常量字段擦除的系统
公开(公告)号：US5805502A
公开(公告)日：1998-09-08
申请号：US795024
申请日：1997-02-04
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

3. 发明授权

US06172915B2 Unified erase method in flash EEPROM 有权
标题翻译：闪存EEPROM中的统一擦除方法
公开(公告)号：US06172915B2
公开(公告)日：2001-01-09
申请号：US09408705
申请日：1999-09-30
申请人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
发明人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C8/12
摘要： A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.
摘要翻译：在用于执行单扇区，多扇区或全扇区擦除操作的闪存EEPROM存储器单元阵列中使用的统一擦除方法，其具有减少的总擦除时间量和均匀的VT分布与单扇区擦除操作一样好。如果其对应的擦除信号没有关闭，则从第一扇区到最后扇区的多个扇区中顺序执行擦除验证操作，从每个扇区的第一地址开始。每个扇区的当前地址存储在擦除验证操作失败的点。擦除脉冲仅对未通过擦除验证操作的所有扇区同时施加。然后从存储的当前地址开始重复擦除验证操作。当在多个扇区的所有扇区中已经关闭了擦除信号时，结束擦除操作。

4. 发明授权

US6023426A Method of achieving narrow V.sub.T distribution after erase in flash EEPROM 失效
标题翻译：在闪存EEPROM中擦除后实现窄VT分布的方法
公开(公告)号：US6023426A
公开(公告)日：2000-02-08
申请号：US36971
申请日：1998-03-09
申请人： Yuan Tang , James C. Yu , Chien-Sheng Su
发明人： Yuan Tang , James C. Yu , Chien-Sheng Su
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/3404
摘要： There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.
摘要翻译：提供了一种在擦除之后校正闪存EEPROM存储单元中的过度存储单元的方法，以产生窄的阈值电压分布宽度。将地电势施加到存储器单元阵列中的所有单元的源和衬底。第一正脉冲电压以字线为单位，以字线的第一定时序列同时施加到每个字线。当第一正脉冲电压被施加到第一字线时，第二正时脉冲电压以位线为单位的第二定时序列同时施加到每个位线，然后对于每个后续字线重复，直到最后一个字线被应用。

5. 发明授权

US06222771B1 Unified program method and circuitry in flash EEPROM 有权
标题翻译：闪存EEPROM中的统一程序方法和电路
公开(公告)号：US06222771B1
公开(公告)日：2001-04-24
申请号：US09494456
申请日：2000-01-31
申请人： Yuan Tang , James C. Yu
发明人： Yuan Tang , James C. Yu
IPC分类号： G11C1606
CPC分类号： G11C16/3481 , G11C11/5628 , G11C16/10 , G11C16/3468 , G11C2211/5624
摘要： A unified program method and circuitry for performing concurrently a programming and verifying operation in an array of Flash EEPROM memory cells is provided. Each of the memory cells includes a floating gate array core transistor. A single bandgap voltage is provided which corresponds to a predetermined amount of drain current at which programming is to be terminated. A program voltage is selectively connected to at least one of the columns of array bit lines containing the array core transistor which is to be programmed. A control gate bias voltage corresponding to a programmable memory state is selectively connected to the gate of the array core transistor. A core cell current flowing through the array core transistor and the predetermined amount of drain current is compared. The program voltage is disconnected so as to terminate automatically programming of the array core transistor when the core cell current falls below the predetermined amount of drain current.
摘要翻译：提供了一种统一的程序方法和电路，用于同时执行闪存EEPROM存储单元阵列中的编程和验证操作。每个存储单元包括浮栅阵列核心晶体管。提供单个带隙电压，其对应于将终止编程的预定量的漏极电流。选择性地将编程电压连接到包含待编程的阵列芯晶体管的阵列位线列中的至少一列。对应于可编程存储器状态的控制栅极偏置电压选择性地连接到阵列核心晶体管的栅极。比较流过阵列核心晶体管的核心单元电流和预定量的漏极电流。程序电压被断开，从而当核心单元电流低于预定的漏极电流量时自动编程阵列核心晶体管。

6. 发明授权

US5485423A Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS 失效
标题翻译：消除5伏隧道氧化物中循环诱导电子捕获的方法，只有闪存EEPROMS
公开(公告)号：US5485423A
公开(公告)日：1996-01-16
申请号：US320368
申请日：1994-10-11
申请人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
发明人： Yuan Tang , Chi Chang , Michael A. Van Buskirk , Chung K. Chang
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
摘要翻译：提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。在整个擦除周期期间，相对较低的正脉冲电压被施加到EEPROM器件的源极区域。同时，在整个擦除周期期间，向EEPROM器件的控制栅极施加负斜坡电压，从而实现从擦除周期开始到擦除周期结束的平均隧道场。

7. 发明授权

US5852582A Non-volatile storage device refresh time detector 失效
标题翻译：非易失性存储设备刷新时间检测器
公开(公告)号：US5852582A
公开(公告)日：1998-12-22
申请号：US801305
申请日：1997-02-18
申请人： Lee E. Cleveland , Yuan Tang , Jonathan Su , Chi Chang , Chung K. Chang
发明人： Lee E. Cleveland , Yuan Tang , Jonathan Su , Chi Chang , Chung K. Chang
IPC分类号： G11C16/28 , G11C16/32 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3431 , G11C16/28 , G11C16/32 , G11C16/3418
摘要： A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.
摘要翻译：用于监视非易失性存储装置中的存储器阵列何时需要刷新的定时装置包括可编程半导体器件和检测装置，用于检测可编程半导体器件上的电荷量何时已降至至多阈值量。在一个实施例中，可编程半导体器件是通过向浮动栅极增加电荷而编程的浮栅晶体管。检测装置监视晶体管的IDS电流，并且当检测到多于可忽略的IDS电流量时，确定阵列刷新时间。

8. 发明授权

US5596531A Method for decreasing the discharge time of a flash EPROM cell 失效
标题翻译：降低闪速EPROM单元的放电时间的方法
公开(公告)号：US5596531A
公开(公告)日：1997-01-21
申请号：US450167
申请日：1995-05-25
申请人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
发明人： David K. Y. Liu , Ming S. Kwan , Chi Chang , Sameer Haddad , Yuan Tang
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： The present invention presents methods for reducing the discharge time of a Flash EPROM cell. In one aspect, a method includes the steps of forcing an ultraviolet voltage threshold, UVV.sub.t, below a discharge threshold voltage, V.sub.t. The method further comprises reducing the UVV.sub.t to about 0 V. Further, the method further comprises the step of reducing a core cell implant of a p-type dopant into a substrate of the cell. In a further aspect, a method for decreasing the discharge time includes the steps of providing a core cell implant of a p-type dopant into a surface of a substrate of the cell, and providing a surface doping of an n-type dopant into the core of the substrate, where the core implant reduces punchthrough and the surface doping of an n-type dopant reduces V.sub.t in the cell. In yet another aspect, a method for decreasing a discharge time of a Flash EPROM cell while reducing punchthrough includes the steps of providing a high energy core cell implant of a p type dopant into a substrate of the cell, wherein the core has a doping concentration profile with a low dopant concentration at a surface of the core to reduce UVV.sub.t and a high dopant concentration at lower than the surface to reduce punchthrough.
摘要翻译：本发明提出了减少闪存EPROM单元的放电时间的方法。在一个方面，一种方法包括以下步骤：将紫外线电压阈值UVVt强制在放电阈值电压Vt以下，该方法还包括将UVVt降低到约0V。此外，该方法还包括如下步骤：将p型掺杂剂细胞注入细胞的底物。在另一方面，一种减少放电时间的方法包括以下步骤：将p型掺杂剂的核心单元注入提供到电池的衬底的表面中，并且向n型掺杂剂表面掺杂衬底的芯部，其中芯体植入物减少穿透并且n型掺杂剂的表面掺杂减小了电池中的Vt。在另一方面，一种减少穿透时减少闪存EPROM单元的放电时间的方法包括以下步骤：将ap型掺杂剂的高能核心单元注入提供到电池的衬底中，其中芯具有掺杂浓度分布在芯的表面处具有低掺杂剂浓度以降低UVVt，并且在低于表面的情况下具有高掺杂剂浓度以减少穿透。

9. 发明授权

US06490203B1 Sensing scheme of flash EEPROM 失效
标题翻译：闪存EEPROM的检测方案
公开(公告)号：US06490203B1
公开(公告)日：2002-12-03
申请号：US09863697
申请日：2001-05-24
申请人： Yuan Tang
发明人： Yuan Tang
IPC分类号： G11C1604
CPC分类号： G11C16/345 , G11C16/28 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459
摘要： There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.
摘要翻译：提供了一种用于在闪存EEPROM存储器核心单元阵列中的选定的存储器核心单元上执行程序验证，擦除验证和过擦除校正验证模式的读取电路和方法。将固定的控制栅极偏置电压施加到其状态将被验证以产生核心单元漏极电流的核心单元晶体管的控制栅极。各种控制栅极偏置电压被施加到单个参考单元晶体管的控制栅极，用于产生对应于预定操作模式的不同参考电流。在第二实施例中，从电流源产生不同的参考电流。

10. 发明授权

US5869385A Selectively oxidized field oxide region 失效
标题翻译：选择性氧化场氧化物区域
公开(公告)号：US5869385A
公开(公告)日：1999-02-09
申请号：US569704
申请日：1995-12-08
申请人： Yuan Tang , Mark Ramsbey
发明人： Yuan Tang , Mark Ramsbey
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/76213 , Y10S148/138 , Y10S438/964
摘要： A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.
摘要翻译：通过选择性地将杂质原子注入到半导体衬底中以增加衬底的氧化速率并对半导体衬底的注入区域进行热氧化，形成具有缩小的鸟嘴的场氧化物区域。在另一个实施例中，通过在要形成栅极氧化物的厚部分并对半导体衬底进行热氧化的选定区域中将杂质原子注入到半导体衬底中，形成具有差分厚度的栅氧化层。

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