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1. 再颁专利

USRE46573E1 Simultaneous multi-state read or verify in non-volatile storage 有权
公开(公告)号：USRE46573E1
公开(公告)日：2017-10-17
申请号：US14285426
申请日：2014-05-22
申请人： SanDisk IL Ltd.
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06 , G11C11/56 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.

2. 发明申请

US20170076802A1 Programming of Nonvolatile Memory with Verify Level Dependent on Memory State and Programming Loop Count 审中-公开
标题翻译：根据存储器状态和编程循环计数验证电平的非易失性存储器的编程
公开(公告)号：US20170076802A1
公开(公告)日：2017-03-16
申请号：US14853733
申请日：2015-09-14
申请人： SanDisk Technologies, LLC.
发明人： Nima Mokhlesi
IPC分类号： G11C16/14 , G11C16/28 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624
摘要： A series of programming pulses, where the individual pulses are identified by a pulse number, is used to program a page of memory cells in parallel. After receiving a pulse, the memory cells under verification are verified to determine if they have been programmed to their respective target states. The memory cells that have been verified are inhibited from further programming while those memory cells not verified will be further programmed by subsequent programming pulses. The pulsing, verification and inhibition continue until all memory cells of the page have been program-verified. Each verify level used in the verification is a function of both the target state and the pulse number. This allows adjustment of the verify level to compensate for changes in sensing, including those due to variation in source line loading during the course of programming.
摘要翻译：使用一系列编程脉冲，其中单个脉冲由脉冲数标识，用于并行编程存储器单元的页面。在接收到脉冲之后，验证的存储器单元被确认以确定它们是否被编程到它们各自的目标状态。已经验证的存储器单元被禁止进一步编程，而未被验证的那些存储器单元将被随后的编程脉冲进一步编程。脉冲，验证和禁止继续，直到页面的所有存储单元已经被程序验证。验证中使用的每个验证级别都是目标状态和脉冲数的函数。这允许调整验证电平以补偿感测变化，包括在编程过程中由于源线负载变化引起的变化。

3. 发明申请

US20160300620A1 MULTIPLE BIT LINE VOLTAGE SENSING FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的多位线电压感测
公开(公告)号：US20160300620A1
公开(公告)日：2016-10-13
申请号：US14817767
申请日：2015-08-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Dana Lee , Ken Oowada , Shih-Chung Lee
IPC分类号： G11C16/34 , G11C16/28 , G11C16/10 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3459 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.
摘要翻译：非易失性存储器系统包括以三维结构排列的多个存储器单元和与存储器单元通信的一个或多个控制电路。一个或多个控制电路被配置为对存储器单元编程和验证编程。一个或多个控制电路被配置为将参考电压施加到存储器单元。在将参考电压施加到多个存储单元的同时，一个或多个控制电路被配置为通过将不同的位线电压施加到连接到多个存储单元的不同位线来检测多个存储单元的不同存储单元是否处于不同的数据状态不同的记忆体。

4. 发明申请

US20140056062A1 SEMICONDUCTOR STORAGE APPARATUS OR SEMICONDUCTOR MEMORY MODULE 审中-公开
标题翻译：半导体存储器件或半导体存储器模块
公开(公告)号：US20140056062A1
公开(公告)日：2014-02-27
申请号：US14070131
申请日：2013-11-01
申请人： Hitachi, Ltd.
发明人： Satoru HANZAWA
IPC分类号： G11C7/22 , G11C13/00
CPC分类号： G11C7/22 , G11C7/1039 , G11C7/1042 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2207/2209 , G11C2207/2245 , G11C2211/5623 , G11C2211/5624
摘要： A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.
摘要翻译：半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。在存储器区域控制电路中激活读出启动信号的期间，并且读出驱动器对的块在上部存储区域中进行验证读取; 激活存储器区域控制电路中的写入使能信号，并且读出锁存器和写入驱动器对的块对下部存储器区域中的数据执行重写操作。这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的可靠性重写操作以及抑制重写操作峰值电流。

5. 发明申请

US20140022855A1 MULTI LEVEL ANTIFUSE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：多层次的防弹记忆装置及其操作方法
公开(公告)号：US20140022855A1
公开(公告)日：2014-01-23
申请号：US13912649
申请日：2013-06-07
申请人： MIN-SOO JANG , Young-hun Seo , Chan-yong Lee
发明人： MIN-SOO JANG , Young-hun Seo , Chan-yong Lee
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C11/5692 , G11C17/18 , G11C2211/5624 , G11C2211/563
摘要： An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.
摘要翻译：反熔丝存储器件包括反熔丝存储单元，参考电流产生单元和比较单元。反熔丝存储单元包括反熔丝。参考电流产生单元提供从多个参考电流中选择的参考电流。比较单元将流过反熔丝的单元电流的强度与参考电流的强度进行比较，并提供与比较结果相对应的输出信号。

6. 发明授权

US08509000B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08509000B2
公开(公告)日：2013-08-13
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同阈值电压进行存储单元的测试。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

7. 发明申请

US20120155162A1 SEMICONDUCTOR STORAGE APPARATUS OR SEMICONDUCTOR MEMORY MODULE 有权
标题翻译：半导体存储器件或半导体存储器模块
公开(公告)号：US20120155162A1
公开(公告)日：2012-06-21
申请号：US13327585
申请日：2011-12-15
申请人： Satoru HANZAWA
发明人： Satoru HANZAWA
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1039 , G11C7/1042 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C2207/2209 , G11C2207/2245 , G11C2211/5623 , G11C2211/5624
摘要： A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.
摘要翻译：半导体存储装置提供具有高速运行，低电流和高可靠性的大容量相变存储器。在存储器区域控制电路中激活读出启动信号的期间，并且读出驱动器对的块在上部存储区域中进行验证读取; 激活存储器区域控制电路中的写入使能信号，并且读出锁存器和写入驱动器对的块对下部存储器区域中的数据执行重写操作。这种类型的操作允许通过在一个存储器区域中执行验证读取同时在其他存储器区域中执行时分重写来消除验证读取所需的时间和时分写入操作所需的时间，以实现更高的可靠性重写操作以及抑制重写操作峰值电流。

8. 发明授权

US07453730B2 Charge packet metering for coarse/fine programming of non-volatile memory 有权
公开(公告)号：US07453730B2
公开(公告)日：2008-11-18
申请号：US11429769
申请日：2006-05-08
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

9. 发明申请

US20070091685A1 EFFICIENT VERIFICATION FOR COARSE/FINE PROGRAMMING OF NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的精细/精细编程的有效验证
公开(公告)号：US20070091685A1
公开(公告)日：2007-04-26
申请号：US11550502
申请日：2006-10-18
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/3454 , G11C16/3481 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

10. 发明申请

US20070058436A1 EFFICIENT VERIFICATION FOR COARSE/FINE PROGRAMMING OF NON VOLATILE MEMORY 有权
标题翻译：非易失性存储器的精细/精细编程的有效验证
公开(公告)号：US20070058436A1
公开(公告)日：2007-03-15
申请号：US11550499
申请日：2006-10-18
申请人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/3454 , G11C16/3481 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

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