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1. 发明授权

US06444539B1 Method for producing a shallow trench isolation filled with thermal oxide 有权
标题翻译：用于生产填充有热氧化物的浅沟槽隔离体的方法
公开(公告)号：US06444539B1
公开(公告)日：2002-09-03
申请号：US09784892
申请日：2001-02-15
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2176
CPC分类号： H01L21/7621 , H01L21/3085 , H01L21/3086 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

2. 发明授权

US06232646B1 Shallow trench isolation filled with thermal oxide 失效
标题翻译：浅沟隔离填充热氧化物
公开(公告)号：US06232646B1
公开(公告)日：2001-05-15
申请号：US09082607
申请日：1998-05-20
申请人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
发明人： Yu Sun , Angela T. Hui , Yue-Song He , Tatsuya Kajita , Mark Chang , Chi Chang , Hung-Sheng Chen
IPC分类号： H01L2900
CPC分类号： H01L21/7621 , H01L21/76232
摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.
摘要翻译：一种用于产生浅沟槽隔离的半导体装置和方法。该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域。随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

3. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

4. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

5. 发明申请

US20080061359A1 Dual charge storage node with undercut gate oxide for deep sub-micron memory cell 审中-公开
标题翻译：具有底切栅极氧化物的双电荷存储节点用于深亚微米存储单元
公开(公告)号：US20080061359A1
公开(公告)日：2008-03-13
申请号：US11702847
申请日：2007-02-05
申请人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
发明人： Chungho Lee , Hiroyuki Kinoshita , Zoran Krivokapic , Wei Zheng , Mark Chang , Rinji Sugino , Chi Chang
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/42348 , H01L29/7885 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括形成在衬底上的堆叠。堆叠包括栅极氧化物层和上覆的多晶硅层。堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

6. 发明授权

US06764929B1 Method and system for providing a contact hole in a semiconductor device 失效
标题翻译：用于在半导体器件中提供接触孔的方法和系统
公开(公告)号：US06764929B1
公开(公告)日：2004-07-20
申请号：US10151625
申请日：2002-05-16
申请人： Angela Hui , Chi Chang , Mark Chang
发明人： Angela Hui , Chi Chang , Mark Chang
IPC分类号： H01L21425
CPC分类号： H01L21/76897 , H01L21/265
摘要： A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures. Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure. Due to the etch difference between the implant treated device and the non-treated surface, it is possible to etch down to the bottom of the semiconductor device without damaging the gate. Since the surface around the gate structure is treated, the etch stop layer etch at a much slower rate. Therefore, there is a much larger process margin for misalignment allowance and the contact size can be larger because the dielectric material and the surface treatment protects the gate area.
摘要翻译：公开了一种用于在半导体器件的结构之间提供接触孔的方法和系统。该方法和系统包括在半导体器件上蚀刻抗蚀剂材料以暴露结构的表面; 向所述结构的表面提供植入物; 以及从结构之间的间隙去除抗蚀剂材料。该方法和系统包括退火半导体器件以使植入物粘附到被处理的表面上; 并在间隙内提供电介质材料。最后，该方法和系统包括蚀刻结构之间的间隙中的接触孔。然后可以蚀刻接触孔而不损坏结构。因此，通过提供植入物处理的表面，然后提供退火工艺，将植入物结合到半导体结构的适当部分。由于植入物处理的设备和未处理的表面之间的蚀刻差异，可以在不损坏栅极的情况下向下蚀刻到半导体器件的底部。由于栅极结构周围的表面被处理，蚀刻停止层以较慢的速率蚀刻。因此，由于介电材料和表面处理保护了栅极区域，所以对于不对准余量有更大的处理余量，并且接触尺寸可以更大。

7. 发明申请

US20050092983A1 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US20050092983A1
公开(公告)日：2005-05-05
申请号：US10699903
申请日：2003-11-03
申请人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
发明人： Christopher Lyons , Mark Chang , Sergey Lopatin , Ramkumar Subramanian , Patrick Cheung , Minh Ngo , Jane Oglesby
IPC分类号： G11C11/56 , G11C13/02 , H01L27/115 , H01L27/28 , H01L29/68 , H01L45/00 , H01L51/00 , H01L29/73
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

8. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

9. 发明授权

US5494271A Transmission system for a document feeder 失效
标题翻译：文件传送系统
公开(公告)号：US5494271A
公开(公告)日：1996-02-27
申请号：US257570
申请日：1994-06-10
申请人： Jeffrey Wun , Steven Chiu , Mark Chang
发明人： Jeffrey Wun , Steven Chiu , Mark Chang
IPC分类号： B65H3/06 , B65H5/06
CPC分类号： B65H3/0669 , Y10T74/19172 , Y10T74/1921
摘要： An improved transmission system for a document feeder, in which a constant one-way-rotating gear train is mounted in an output zone so as to cause a transmission shaft in the output zone to rotate in one direction only to send out a sheet of document no matter the driving gear rotates clockwise or counter-clockwise; therefore, as soon as a first sheet of document moves out of the scanning line without moving out of the output zone, the driving gear will change its rotation clockwise so as to have a next sheet of document fed into the scanning zone; therefore, the feeding distance between two sheets of document will be reduced, and consequently the whole feeding time for a document will be reduced, too.
摘要翻译：一种用于文件馈送器的改进的传输系统，其中恒定的单向旋转齿轮系安装在输出区域中，以便使得输出区域中的传动轴在一个方向上旋转，仅发出一张文件无论主动齿轮顺时针还是逆时针旋转; 因此，只要第一张原稿从扫描线移出而不移出输出区域，驱动齿轮将顺时针转动其旋转，以便将下一张原稿送入扫描区域; 因此，两纸张之间的进纸距离将减小，因此文件的整个进纸时间也将减少。

10. 发明授权

US08035153B2 Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜和蚀刻用于闪存和其他半导体应用的自对准图案化方法
公开(公告)号：US08035153B2
公开(公告)日：2011-10-11
申请号：US12788177
申请日：2010-05-26
申请人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
发明人： Shenqing Fang , Jihwan Choi , Calvin Gabriel , Fei Wang , Angela Hui , Alexander Nickel , Zubin Patel , Phillip Jones , Mark Chang , Minh-Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/11568
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。然后在核心单元之间完全或部分蚀刻捕获层。去除非保形膜。并形成顶部氧化物。如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

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